General Description: This solution describes a procedure for integrating CORE Generator modules into Summit Visual HDL designs. It is based on informal input from the field and has not been verified yet by Xilinx Applications.
3.1i and 2.1i CORE Generator, VHDL Flow: -------------------------------------------------------------------- With the 3.1i /2.1i CORE Generator VHDL flow, which utilizes VHDL configuration), you must do the following:
1. Declare the VHDL configuration for the design in a separate .VHD file. The VHDL configuration in this file should reference all the entities for the CORE Generator models in your design. This is especially helpful if you are using several cores in your design.
2. Within Summit, create a wrapper for each core you are instantiating. For example, if you have a filter core, you would create a block in Summit with an entity and an architecture. The architecture would call out a component declaration for the core, and in the body of the architecture you would have a component instantiation of the core.
3. Within Summit, perform a "Create a VHDL netlist" operation for the design.
In the 3.1i/2.1i CORE Generator flow, there is no VHDL netlist for cores generated in a project, so Summit simply creates a top level VHDL netlist with a place holder for each core component and issues a warning that no such components exist.
4. In MTI (or other simulation tool), compile the XilinxCoreLib library according to the order specified in the vhdl_analyze_order file (located in $XILINX/vhdl/src/XilinxCoreLib). Next, compile the VHDL netlist produced by Summit. Finally, compile the test bench and configuration file (make sure the configuration file has a .vhd extension).
You are now ready run the simulation. To simulate, load the VHDL CONFIGURATION for the testbench (not the Architecture!).
5. For synthesis, just synthesize the VHDL netlist generated by Summit. Nothing needs to be done with the configuration file since it is only there to support functional simulation.
For cores generated using CORE Generator 1.5 and earlier, you would have behavioral models for each individual core in your project directory. In this case, the procedure is as follows:
1. Instantiate the cores without a wrapper, the same way you would for any other type of VHDL component.
2. Create a library of core models. For example, if the cores were all 4K cores, you might call the library, "4k_cores".
3. To create the VHDL netlist, select Options-> HDL Generator-> Skip Libraries-> (select the library that contains the core models). Summit will then create the VHDL netlist for the design with place holders for the core components.
4. Compile the VHDL netlist and applicable libraries (there are no VHDL configurations or XilinxCoreLib library in this case), then run Simulation.
5. Synthesize the Summit VHDL netlist for the design.