AR# 9578: 3.1i Foundation ISE: ECS Schematic with instantiated Verilog macros(CORE Generator) fails in XST
AR# 9578
3.1i Foundation ISE: ECS Schematic with instantiated Verilog macros(CORE Generator) fails in XST
説明
Keywords: ECS, CORE Generator, verilog
Urgency: Standard
General Description: When a Verilog design is synthesized and instantiated modules have not been declared, the following error message is issued by XST:
ERROR : (VLG__5002). stopwatch.v Line 44. Module 'tenths' not defined
ECS schematic designs containing CORE Generator macros are not declared by default. The module definition must be added to the project.
ソリューション
Rename the <core>.veo file to <core>.v and add it to the project.