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AR# 9622

3.1i UNISIMS, SIMPRIMS - CLKDLL's Clk2x output has a 25% duty cycle


Unisims, Simprims, CLKDLL, duty, cycle, 25%, 75%, clk2x

Urgency: Standard

General Description:
For a CLKDLL simulation, the CLK0 output is correct, but the
CLK2X output is not doubled and has a duty cycle of 25%.


Until the CLKDLL has locked (LOCKED signal high),
the 2x output will be incorrectly displayed. Wait for
the LOCKED signal to go high before using the
CLK2X clock in the design.

To ensure a lock, simulation should be run at the
ps resolution, 'VSIM -t ps' and the CLKDLL should
initially be reset.
AR# 9622
日付 08/25/2003
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