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AR# 9702

FPGA Express 3.3 - Can attributes be added to signal/nets in HDL code?

説明

Keywords: Attributes, signals, HDL, nets

Urgency: Standard

General Description:
Can attributes be placed on nets/signal in HDL code?

ソリューション

VHDL:

Attributes can be placed on components only.

Verilog:

Attributes can be placed on ports and modules.

See (Xilinx Solution 4392) for information on passing attributes.
AR# 9702
日付 08/11/2003
ステータス アーカイブ
種類 一般