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AR# 9774

VSS : How do I simulate Xilinx designs in VSS? (VHDL)

説明

Keywords:
Synopsys, VSS, vhdlan, vhdlsim, simulation, how

Urgency: Standard

General Description:

How do I simulate Xilinx designs
in Synopsys VSS?

ソリューション

1



VSS requires a WORK directory to put
the compiled data in. First, create
the WORK directory in the project
directory as follows:

mkdir WORK

Make sure the following line is
added to the .synopsys_vss.setup
file:

WORK: /path_to_directory/WORK

Run the following command to
compile the files:
vhdlan -i file1.vhd file2.vhd
vhdlan -i testbench.vhd

The following command will
load the simulation:
vhdlsim -e commandfile.txt cfg_tstbench

where commandfile.txt contains the commands
to start up the waveform viewer, add signals
and stimulus. For more information on the
commandfile.txt, consult Synopsys VSS
documentation.

2

For information on how to compile Xilinx libraries for
VSS, see solution 9755 at
http://www.xilinx.com/techdocs/9755.htm
AR# 9774
作成日 08/31/2007
最終更新日 10/01/2008
ステータス アーカイブ
タイプ 一般