Does Xilinx produce timing simulation information for various I/O standards and capacitive loading?
All Xilinx timing information uses a default capacitive loading value. This value varies depending on the I/O standard used, but is typically 0pF. For specific I/O standards, please refer to the appropriate data sheet at:
However, if a different capacitive load value is used, you must adjust the I/O timing to take this into account. Please refer to (Xilinx Answer 17720) for more information.