Performance AXI Traffic Generator LogiCORE IP Product Guide (PG381) - 1.0 English

Document ID: PG381
Release Date: 2023-10-18
Version: 1.0 English

IP Core Overview
Introduction
Features
AXI3/AXI4 Features
AXI4-Stream Features
IP Facts
Navigating Content by Design Process
Licensing and Ordering
Synthesizable TG
Overview
Core Overview
Modes of Operation
CSV Command Format
Simulation Trigger for the NoC AXI TG
Dynamic Operating Mode
High-Level Architecture
Synthesizable Traffic Generator Architecture
Synthesizable AXI4 Architecture
Synthesizable AXI4-Stream Architecture
Product Specification
Port Descriptions
Synthesizable TG
Data Integrity Modes
Data Integrity Check
Constant ID (In-Order) Traffic
Incremental ID (Out-of-Order) Traffic
Delays Supported by the TG
AXI3/AXI4 and AXI4-Stream
Parity Generation
Performance Counters
Synchronization of Multiple TGs
Traffic Shaping
Simulation Trigger Module with Multiple TGs
Hardware Access
AXI4-Lite Interface
VIO Interface
Register Space
Address Decoding for Synthesizable TG
Register Space Addressing: 0x0000 to 0x7FFC
Block RAM Addressing: 0x8000 to 0xFFFC
AXI3/AXI4 Configuration Registers
SOFT_RST Register (0x4000)
TG_START Register (0x4004)
OUTSTND_RESP_LIMIT Register (0x4010)
DI_MASK_BYTES_1 Register (0x41A8)
DI_MASK_BYTES_2 Register (0x41AC)
CAPTURE_ENABLE (0x42D0)
START_ADDR (0x42D4)
END_ADDR (0x42D8)
TG_PAUSE (0x42F4)
AXI3/AXI4 Status Registers
RBEAT_COUNTER Register (0x2014)
ARREQ_COUNTER Register (0x2018)
RLAST_CNTR Register (0x201C)
RBW_EFF_CLK_CNTR Register (0x2020)
RWORST_LATENCY Register (0x2014)
RBEST_LATENCY Register (0x2028)
RAVG_LATENCY Register (0x202C)
AWREQ_CNTR Register (0x2030)
WLAST_CNTR Register (0x2034)
BRESP_CNTR Register (0x2038)
WRBEAT_CNTR Register (0x203C)
WBW_EFF_CLK_CNTR Register (0x2040)
WWORST_LATENCY Register (0x2044)
WBEST_LATENCY Resgister (0x2048)
WAVG_LATENCY Register (0x204C)
FLOW_EMPTY Register (0x2050)
DI_ERR_COUNT Register (0x2054)
DI_ERR_ADDR0_LSB_0 Register (0x2058)
DI_ERR_ADDR0_MSB16_0 Register (0x205C)
DI_ERR_TXN_INFO_0 Register (0x2060)
DI_ERR_ADDR0_LSB_1 Register (0x2064)
DI_ERR_ADDR0_MSB16_1 Register (0x2068)
DI_ERR_TXN_INFO_1 Register (0x206C)
DI_ERR_ADDR0_LSB_2 Register (0x2070)
DI_ERR_ADDR0_MSB16_2 Register (0x2074)
DI_ERR_TXN_INFO_2 Register (0x2078)
DI_ERR_ADDR0_LSB_3 Register (0x207C)
DI_ERR_ADDR0_MSB16_3 Register (0x2080)
DI_ERR_TXN_INFO_3 Register (0x2084)
DI_ERR_ADDR0_LSB_4 Register (0x2088)
DI_ERR_ADDR0_MSB16_4 Register (0x208C)
DI_ERR_TXN_INFO_4 Register (0x2090)
DI_ERR_ADDR0_LSB_5 Register (0x2094)
DI_ERR_ADDR0_MSB16_5 Register (0x2098)
DI_ERR_TXN_INFO_5 Register (0x209C)
DI_ERR_ADDR0_LSB_6 Register (0x20A0)
DI_ERR_ADDR0_MSB16_6 Register (0x20A4)
DI_ERR_TXN_INFO_6 Register (0x20A8)
DI_ERR_ADDR0_LSB_7 Register (0x20AC)
DI_ERR_ADDR0_MSB16_7 Register (0x20B0)
DI_ERR_TXN_INFO_7 Register (0x20B4)
DI_ERR_ADDR0_LSB_8 Register (0x20B8)
DI_ERR_ADDR0_MSB16_8 Register (0x20BC)
DI_ERR_TXN_INFO_8 Register (0x20C0)
DI_ERR_ADDR0_LSB_9 Register (0x20C4)
DI_ERR_ADDR0_MSB16_9 Register (0x20C8)
DI_ERR_TXN_INFO_9 Register (0x20CC)
BRESP_EXOKAY_CNTR Register (0x20D0)
BRESP_SLVERR_CNTR Register (0x20D4)
BRESP_DECERR_CNTR Register (0x20D8)
RCVD_RDATA_ACT_0T31 Register (0x20DC)
RCVD_RDATA_ACT_32T63 Register (0x20E0)
RCVD_RDATA_ACT_64T95 Register (0x20E4)
RCVD_RDATA_ACT_96T127 Register (0x20E8)
RCVD_RDATA_ACT_128T159 Register (0x20EC)
RCVD_RDATA_ACT_160T191 Register (0x20F0)
RCVD_RDATA_ACT_192T223 Register (0x20F4)
RCVD_RDATA_ACT_255T224 Register (0x20F8)
RCVD_RDATA_ACT_287T256 Register (0x20FC)
RCVD_RDATA_ACT_319T288 Register (0x2100)
RCVD_RDATA_ACT_351T320 Register (0x2104)
RCVD_RDATA_ACT_383T352 Register (0x2108)
RCVD_RDATA_ACT_ 015T384 Register (0x210C)
RCVD_RDATA_ACT_447T416 Register (0x2110)
RCVD_RDATA_ACT_479T448 Register (0x2114)
RCVD_RDATA_ACT_511T480 Register (0x2118)
RCVD_RDATA_EXPD_0T31 Register (0x211C)
RCVD_RDATA_EXPD_32T63 Register (0x2120)
RCVD_RDATA_EXPD_64T95 Register (0x2124)
RCVD_RDATA_EXPD_96T127 Register (0x2128)
RCVD_RDATA_EXPD_128T159 Register (0x212C)
RCVD_RDATA_EXPD_160T191 Register (0x2130)
RCVD_RDATA_EXPD_192T223 Register (0x2134)
RCVD_RDATA_EXPD_255T224 Register (0x2138)
RCVD_RDATA_EXPD_287T256 Register (0x213C)
RCVD_RDATA_EXPD_319T288 Register (0x2140)
RCVD_RDATA_EXPD_351T320 Register (0x2144)
RCVD_RDATA_EXPD_383T352 Register (0x2148)
RCVD_RDATA_EXPD_415T384 Register (0x214C)
RCVD_RDATA_EXPD_447T416 Register (0x2150)
RCVD_RDATA_EXPD_479T448 Register (0x2154)
RCVD_RDATA_EXPD_511T480 Register (0x2158)
LAST_RDATA_RCVD_0T31 Register (0x215C)
LAST_RDATA_RCVD_32T63 Register (0x2160)
LAST_RDATA_RCVD_64T95 Register (0x2164)
LAST_RDATA_RCVD_96T127 Register (0x2168)
LAST_RDATA_RCVD_128T159 Register (0x216C)
LAST_RDATA_RCVD_160T191 Register (0x2170)
LAST_RDATA_RCVD_192T223 Register (0x2174)
LAST_RDATA_RCVD_255T224 Register (0x2178)
LAST_RDATA_RCVD_287T256 Register (0x217C)
LAST_RDATA_RCVD_319T288 Register (0x2180)
LAST_RDATA_RCVD_351T320 Register (0x2184)
LAST_RDATA_RCVD_383T352 Register (0x2188)
LAST_RDATA_RCVD_415T384 Register (0x218C)
LAST_RDATA_RCVD_447T416 Register (0x2190)
LAST_RDATA_RCVD_479T448 Register (0x2194)
LAST_RDATA_RCVD_511T480 Register (0x2198)
RRESP_EXOKAY_CNTR Register (0x219C)
RRESP_SLVERR_CNTR Register (0x21A0)
RRESP_DECERR_CNTR Register (0x21A4)
AXI_VLD_RDY_STATS Register (0x21B0)
BRESP_ERR_COUNT Register (0x21B8)
BRESP_ERR_ADDR0_LSB_0 Register (0x21BC)
BRESP_ERR_ADDR0_MSB16_0 Register (0x21C0)
BRESP_ERR_TXN_INFO_0 Register (0x21C4)
BRESP_ERR_ADDR0_LSB_1 Register (0x21C8)
BRESP_ERR_ADDR0_MSB16_1 Register (0x21CC)
BRESP_ERR_TXN_INFO_1 Register (0x21D0)
BRESP_ERR_ADDR0_LSB_2 Register (0x21D4)
BRESP_ERR_ADDR0_MSB16_2 Register (0x21D8)
BRESP_ERR_TXN_INFO_2 Register (0x21DC)
BRESP_ERR_ADDR0_LSB_3 Register (0x21E0)
BRESP_ERR_ADDR0_MSB16_3 Register (0x21E4)
BRESP_ERR_TXN_INFO_3 Register (0x21E8)
BRESP_ERR_ADDR0_LSB_4 Register (0x21F0)
BRESP_ERR_ADDR0_MSB16_4 Register (0x21F4)
BRESP_ERR_TXN_INFO_4 Register (0x21F8)
BRESP_ERR_ADDR0_LSB_5 Register (0x21FC)
BRESP_ERR_ADDR0_MSB16_5 Register (0x2200)
BRESP_ERR_TXN_INFO_5 Register (0x2204)
BRESP_ERR_ADDR0_LSB_6 Register (0x2208)
BRESP_ERR_ADDR0_MSB16_6 Register (0x220C)
BRESP_ERR_TXN_INFO_6 Register (0x2210)
BRESP_ERR_ADDR0_LSB_7 Register (0x2214)
BRESP_ERR_ADDR0_MSB16_7 Register (0x2218)
BRESP_ERR_TXN_INFO_7 Register (0x221C)
BRESP_ERR_ADDR0_LSB_8 Register (0x2220)
BRESP_ERR_ADDR0_MSB16_8 Register (0x2224)
BRESP_ERR_TXN_INFO_8 Register (0x2228)
BRESP_ERR_ADDR0_LSB_9 Register (0x222C)
BRESP_ERR_ADDR0_MSB16_9 Register (0x2230)
BRESP_ERR_TXN_INFO_9 Register (0x2234)
CAPTURE_ALL Register (0x2234)
RBEAT_COUNTER_AL Register (0x2238)
ARREQ_COUNTER_AL Register (0x223C)
RLAST_CNTR_AL Register (0x2240)
RBW_EFF_CLK_CNTR_AL Register (0x2244)
RWORST_LATENCY_AL Register (0x2248)
RBEST_LATENCY_AL Register (0x224C)
RAVG_LATENCY_AL Register (0x2250)
AWREQ_CNTR_AL Register (0x2254)
WLAST_CNTR_AL Register (0x2258)
BRESP_CNTR_AL Register (0x225C)
WRBEAT_CNTR_AL Register (0x2260)
WBW_EFF_CLK_CNTR_AL Register (0x2264)
WWORST_LATENCY_AL Register (0x2268)
WBEST_LATENCY_AL Register (0x226C)
WAVG_LATENCY_AL Register (0x2270)
FLOW_EMPTY_AL Register (0x2274)
BRESP_EXOKAY_CNTR_AL Register (0x2278)
BRESP_SLVERR_CNTR_AL Register (0x227c)
BRESP_DECERR_CNTR_AL Register (0x2280)
RRESP_EXOKAY_CNTR_AL Register (0x2284)
RRESP_SLVERR_CNTR_AL Register (0x2288)
RRESP_DECERR_CNTR_AL Register (0x228C)
LAST_RDATA_RCVD_0T31_AL Register (0x2290)
LAST_RDATA_RCVD_32T63_AL Register (0x2294)
LAST_RDATA_RCVD_64T95_AL Register (0x2298)
LAST_RDATA_RCVD_96T127_AL Register (0x229C)
LAST_RDATA_RCVD_128T159_AL Register (0x22A0)
LAST_RDATA_RCVD_160T191_AL Register (0x22A4)
LAST_RDATA_RCVD_192T223_AL Register (0x22A8)
LAST_RDATA_RCVD_255T224_AL Register (0x22AC)
LAST_RDATA_RCVD_287T256_AL Register (0x22B0)
LAST_RDATA_RCVD_319T288_AL Register (0x22B4)
LAST_RDATA_RCVD_351T320_AL Register (0x22B8)
LAST_RDATA_RCVD_383T352_AL Register (0x22BC)
LAST_RDATA_RCVD_415T384_AL Register (0x22C0)
LAST_RDATA_RCVD_447T416_AL Register (0x22C4)
LAST_RDATA_RCVD_479T448_AL Register (0x22C8)
LAST_RDATA_RCVD_511T480_AL Register (0x22CC)
CAPTR_WRBEAT (0x22DC)
CAPTR_RDBEAT (0x22E0)
AXI4-Stream Configuration Registers
START Register (0X4004)
RESET Register (0X4008)
PLAY_PAUSE Register (0x401C)
STROBE LSB BITS Register (0x4020)
STROBE MSB BITS Register (0x4024)
KEEP LSB BITS Register (0x4028)
KEEP MSB BITS Register (0x402C)
AXI4-Stream Status Registers
BANDWIDTH_COUNTER Register (0X200C)
REQUEST_COUNTER Register (0X2010)
TXN_COMPLETE Register (0x2014)
BEAT_COUNTER Register (0x2018)
Designing with the Core
Clocking
Resets
User Guidelines
User Guidelines Specific to AXI4
User Guidelines Specific to AXI4-Stream
Using the Traffic Generators
CSV File Run for the Synthesizable TG
Simulation
Hardware
Running Custom Traffic for the Synthesizable TG
Hardware
Design Flow Steps
Customizing and Generating the Core
Configuration Tab
Synthesizable TG Options Tab
Simulation Trigger for the NoC AXI TG IP
Simulation Trigger Component Configuration Tab
Output Generation
CSV Format for Multiple TGs
Dedicated CSV for Each TG
Common CSV Input for All TGs
Creating a Custom CSV
AXI4 Traffic Pattern CSV Format
WRITE Command
READ Command
WAIT Command
START_LOOP/END_LOOP
PHASE_DONE Command
SET_DEFAULT and DISPLAY Commands
AXI4-Stream Traffic Pattern CSV
STREAM Command
WAIT Command
START_LOOP/END_LOOP
PHASE_DONE Command
SET_DEFAULT and DISPLAY Commands
CSV Command Usage Examples for AXI4
Wait Command
Write Command
Read Command
Loop Command (START_LOOP/END_LOOP)
Infinite Loop
CSV Command Usage Examples for AXI4-Stream
Stream Command
Wait Command
Loop Command (START_LOOP/END_LOOP)
Data Patterns
Data patterns for AXI4
Data patterns for AXI4-Stream
Traffic Pattern through Instruction Format
AXI3/AXI4 Instruction Format
AXI4-Stream Instruction Format
Constraining the Core
Simulation
Synthesis and Implementation
Non-Synthesizable TG
Overview
Modes of Operation
CSV Command Format
Fixed Operating Mode
High-Level Architecture
Product Specification
Port Description
Data Integrity Modes
Additional Considerations for Non-Synthesizable TG Data Integrity Checks
Delays supported by the TG
Parity Generation
Performance Monitoring
Designing with the Core
Clocking
Resets
User Guidelines
User Guidelines Specific to AXI3/AXI4
User Guidelines Specific to AXI4-Stream
Using the Traffic Generator
Test Status Report
AXI3/AXI4 Test
AXI4-Stream Test
Design Flow Steps
Customizing and Generating the Core
Configuration Tab
Non-Synthesizable TG Options Tab
Simulation Trigger for the NoC AXI TG IP
Simulation Trigger Component Configuration Tab
CSV Format for Multiple TGs
Dedicated CSV for Each TG
Common CSV Input for All TGs
AXI3/AXI4 Traffic Pattern CSV Format
WRITE Command
READ Command
WAIT Command
START_LOOP/END_LOOP
PHASE_DONE Command
SET_DEFAULT Command
DISPLAY Command
AXI4 Stream Traffic Pattern CSV Format
STREAM Command
WAIT Command
START_LOOP/END_LOOP
PHASE_DONE Command
SET_DEFAULT Command
DISPLAY Command
CSV Command Usage Examples for AXI3/AXI4
Wait Command
Write Command
Read Command
Loop Command (START_LOOP/END_LOOP)
Infinite Loop
CSV Command Usage Examples for AXI4-Stream
Stream Command
Wait Command
Loop Command (START_LOOP/END_LOOP)
Data Patterns
Data patterns for AXI3/AXI4
Data Patterns for AXI4-Stream
Simulation
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the Traffic Generator
Technical Support
Additional Resources and Legal Notices
Support Resources
Finding Additional Documentation
References
Revision History
Please Read: Important Legal Notices

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