Performance and Resource Utilization for Discrete Fourier Transform v4.1

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_d16_area_1536 16 Area false true CLK 341 3691 4576 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d16_area_no1536 16 Area false false CLK 341 3696 4614 16 3 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d16_spd_1536 16 Speed false true CLK 341 3691 4576 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d16_spd_no1536 16 Speed false false CLK 341 3696 4614 16 3 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d8_area_1536 8 Area false true CLK 314 2871 3483 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d8_area_no1536 8 Area false false CLK 352 2954 3583 16 3 4 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_d16_area_1536 16 Area false true CLK 396 3485 4622 16 4 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d16_area_no1536 16 Area false false CLK 402 3503 4745 16 3 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d16_spd_1536 16 Speed false true CLK 396 3485 4622 16 4 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d16_spd_no1536 16 Speed false false CLK 402 3503 4745 16 3 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d8_area_1536 8 Area false true CLK 396 2818 3598 16 4 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d8_area_no1536 8 Area false false CLK 407 2845 3498 16 3 4 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_d16_area_1536 16 Area false true CLK 560 3832 5053 16 4 4 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_d16_area_no1536 16 Area false false CLK 560 3869 4939 16 3 4 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_d16_spd_1536 16 Speed false true CLK 560 3832 5053 16 4 4 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_d16_spd_no1536 16 Speed false false CLK 560 3869 4939 16 3 4 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_d8_area_1536 8 Area false true CLK 560 3077 3795 16 4 4 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_d8_area_no1536 8 Area false false CLK 555 3074 3684 16 3 4 PRODUCTION 1.23 03-18-2019

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_d16_area_1536 16 Area false true CLK 336 3650 4685 16 4 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d16_area_no1536 16 Area false false CLK 347 3694 4595 16 3 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d16_spd_1536 16 Speed false true CLK 336 3650 4685 16 4 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d16_spd_no1536 16 Speed false false CLK 347 3694 4595 16 3 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d8_area_1536 8 Area false true CLK 347 2954 3483 16 4 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d8_area_no1536 8 Area false false CLK 347 2951 3487 16 3 4 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_d16_area_1536 16 Area false true CLK 374 3458 4584 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d16_area_no1536 16 Area false false CLK 385 3467 4801 16 3 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d16_spd_1536 16 Speed false true CLK 374 3458 4584 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d16_spd_no1536 16 Speed false false CLK 385 3467 4801 16 3 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d8_area_1536 8 Area false true CLK 396 2818 3554 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d8_area_no1536 8 Area false false CLK 407 2849 3566 16 3 4 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_d16_area_1536 16 Area false true CLK 560 3866 4983 16 4 4 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_d16_area_no1536 16 Area false false CLK 560 3854 5012 16 3 4 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_d16_spd_1536 16 Speed false true CLK 560 3866 4983 16 4 4 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_d16_spd_no1536 16 Speed false false CLK 560 3854 5012 16 3 4 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_d8_area_1536 8 Area false true CLK 566 3093 3825 16 4 4 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_d8_area_no1536 8 Area false false CLK 566 3115 3837 16 3 4 PRODUCTION 1.23 03-18-2019

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_d16_area_1536 16 Area false true CLK 566 3846 4811 16 4 4 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_d16_area_no1536 16 Area false false CLK 566 3893 4973 16 3 4 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_d16_spd_1536 16 Speed false true CLK 566 3846 4811 16 4 4 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_d16_spd_no1536 16 Speed false false CLK 566 3893 4973 16 3 4 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_d8_area_1536 8 Area false true CLK 549 2944 3922 16 4 4 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_d8_area_no1536 8 Area false false CLK 571 3107 3757 16 3 4 PRODUCTION 1.25 05-09-2019

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