Performance and Resource Utilization for Divider Generator v5.1

Vivado Design Suite Release 2020.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 396 238 441 7 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 396 589 1208 13 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 396 927 1827 16 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 72 713 267 16 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 456 17 103 2 3 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 440 1280 3334 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 615 125 262 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 483 119 207 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 533 64 134 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 456 219 457 7 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 456 505 1208 13 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 456 799 1827 16 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 95 682 250 16 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 424 18 127 2 3 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 467 1278 3334 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 647 123 264 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 522 118 207 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 577 62 134 0 0 0 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 571 223 443 7 0 1 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 571 535 1208 13 0 1 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 571 858 1829 16 0 1 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 131 681 250 16 0 1 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 625 18 127 2 3 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 806 1279 3334 0 0 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 872 124 264 0 0 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 833 116 209 0 0 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 839 62 136 0 0 0 PRODUCTION 1.28 02-27-2020

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 396 241 441 7 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 396 589 1208 13 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 396 927 1827 16 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 72 715 267 16 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 456 17 103 2 3 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 450 1280 3334 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 615 125 264 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 461 119 207 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 522 64 134 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 456 217 441 7 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 456 507 1208 13 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 456 799 1830 16 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 95 680 250 16 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 424 18 127 2 3 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 407 1280 3334 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 653 123 262 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 527 119 207 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 588 62 136 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 571 220 443 7 0 1 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 571 536 1208 13 0 1 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 571 857 1827 16 0 1 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 131 683 250 16 0 1 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 642 18 127 2 3 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 680 1279 3334 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 872 123 262 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 785 117 207 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 872 62 137 0 0 0 PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 571 220 443 7 0 1 PRODUCTION 1.27 02-28-2020
xczu9eg ffvb1156 -1 zup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 571 536 1208 13 0 1 PRODUCTION 1.27 02-28-2020
xczu9eg ffvb1156 -1 zup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 571 858 1827 16 0 1 PRODUCTION 1.27 02-28-2020
xczu9eg ffvb1156 -1 zup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 131 682 250 16 0 1 PRODUCTION 1.27 02-28-2020
xczu9eg ffvb1156 -1 zup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 642 18 127 2 3 0 PRODUCTION 1.27 02-28-2020
xczu9eg ffvb1156 -1 zup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 817 1279 3334 0 0 0 PRODUCTION 1.27 02-28-2020
xczu9eg ffvb1156 -1 zup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 872 123 262 0 0 0 PRODUCTION 1.27 02-28-2020
xczu9eg ffvb1156 -1 zup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 817 112 209 0 0 0 PRODUCTION 1.27 02-28-2020
xczu9eg ffvb1156 -1 zup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 872 61 136 0 0 0 PRODUCTION 1.27 02-28-2020

COPYRIGHT

Copyright 2020 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.