Resource Utilization for JESD204 v7.2

Vivado Design Suite Release 2018.3

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Artix-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs GTPE2_CHANNEL Speedfile Status
xc7a200t ffg1156 -2 GTPE2_rx_1lane 0 1 1024 0 4 100 rx_core_clk=78 s_axi_aclk=100 1365 1171 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_rx_2lane 0 2 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 2323 1933 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_rx_3lane 0 3 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 3184 2695 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_rx_4lane 0 4 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 4106 3456 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_rx_5lane 0 5 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 5007 4218 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_rx_6lane 0 6 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 5784 4979 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_rx_7lane 0 7 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 6665 5740 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_rx_8lane 0 8 1024 0 false 0 4 100 rx_core_clk=78 s_axi_aclk=100 7755 6501 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_tx_1lane 1 1 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1277 912 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_tx_2lane 1 2 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1494 1179 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_tx_3lane 1 3 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1736 1430 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_tx_4lane 1 4 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 1975 1681 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_tx_5lane 1 5 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2223 1932 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_tx_6lane 1 6 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2443 2183 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_tx_7lane 1 7 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2697 2434 0 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 -2 GTPE2_tx_8lane 1 8 0 false false false 0 4 100 s_axi_aclk=100 tx_core_clk=78 2939 2685 0 0 0 0 PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs GTXE2_CHANNEL BUFG Speedfile Status
xc7k325t ffg900 -2 GTXE2_rx_1lane 0 1 1024 0 0 100 rx_core_clk=156 s_axi_aclk=100 1373 1193 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_2lane 0 2 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 2334 1955 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_3lane 0 3 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 3192 2717 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_4lane 0 4 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 4085 3478 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_5lane 0 5 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 4933 4240 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_6lane 0 6 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 5790 5001 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_7lane 0 7 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 6676 5762 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_rx_8lane 0 8 1024 0 false 0 0 100 rx_core_clk=156 s_axi_aclk=100 7765 6523 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_1lane 1 1 1 false false false 0 0 100 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/RXOUTCLK=156 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/RXOUTCLKFABRIC=156 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/TXOUTCLK=156 DUT/inst/i_jesd204_phy/inst/jesd204_phy_block_i/my_ip_phy_gt/inst/my_ip_phy_gt_i/gt0_my_ip_phy_gt_i/gtxe2_i/TXOUTCLKFABRIC=156 refclk_p=156 s_axi_aclk=100 1517 1265 0 0 0 1 1 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_2lane 1 2 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 1503 1201 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_3lane 1 3 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 1747 1452 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_4lane 1 4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 1984 1703 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_5lane 1 5 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2236 1954 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_6lane 1 6 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2447 2205 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_7lane 1 7 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2712 2456 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -2 GTXE2_tx_8lane 1 8 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=156 2944 2707 0 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs GTHE3_CHANNEL Speedfile Status
xcku040 ffva1156 -2 GTHE3_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1323 1171 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_rx_2lane 0 2 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 2283 1933 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_rx_3lane 0 3 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 3160 2695 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_rx_4lane 0 4 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 4069 3456 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_rx_5lane 0 5 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 4964 4218 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_rx_6lane 0 6 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 5717 4979 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_rx_7lane 0 7 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 6576 5740 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_rx_8lane 0 8 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 7514 6501 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_tx_1lane 1 1 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1289 921 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_tx_2lane 1 2 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1511 1172 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_tx_3lane 1 3 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1737 1423 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_tx_4lane 1 4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1980 1674 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_tx_5lane 1 5 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2212 1925 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_tx_6lane 1 6 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2437 2176 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_tx_7lane 1 7 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2684 2427 0 0 0 0 PRODUCTION 1.25 10-29-2018
xcku040 ffva1156 -2 GTHE3_tx_8lane 1 8 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2918 2678 0 0 0 0 PRODUCTION 1.25 10-29-2018

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs GTHE2_CHANNEL Speedfile Status
xc7vx690t ffg1761 -2 GTHE2_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1364 1171 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_2lane 0 2 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 2317 1933 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_3lane 0 3 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 3183 2695 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_4lane 0 4 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 4106 3456 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_5lane 0 5 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 5008 4218 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_6lane 0 6 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 5783 4979 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_7lane 0 7 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 6663 5740 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_rx_8lane 0 8 1024 0 false 0 0 100 rx_core_clk=200 s_axi_aclk=100 7753 6501 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_1lane 1 1 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1275 912 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_2lane 1 2 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1494 1179 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_3lane 1 3 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1733 1430 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_4lane 1 4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1973 1681 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_5lane 1 5 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2222 1932 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_6lane 1 6 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2442 2183 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_7lane 1 7 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2695 2434 0 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -2 GTHE2_tx_8lane 1 8 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2934 2685 0 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs GTYE4_CHANNEL Speedfile Status
xcvu3p ffvc1517 -2 GTYE4_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1324 1171 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_rx_2lane 0 2 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 2286 1933 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_rx_3lane 0 3 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 3159 2695 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_rx_4lane 0 4 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4066 3456 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_rx_5lane 0 5 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4962 4218 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_rx_6lane 0 6 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 5716 4979 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_rx_7lane 0 7 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 6575 5740 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_rx_8lane 0 8 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 7518 6501 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_tx_1lane 1 1 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1289 921 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_tx_2lane 1 2 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1510 1172 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_tx_3lane 1 3 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1738 1423 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_tx_4lane 1 4 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1977 1674 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_tx_5lane 1 5 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2214 1925 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_tx_6lane 1 6 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2437 2176 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_tx_7lane 1 7 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2682 2427 0 0 0 0 PRODUCTION 1.23 10-29-2018
xcvu3p ffvc1517 -2 GTYE4_tx_8lane 1 8 GTYE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2917 2678 0 0 0 0 PRODUCTION 1.23 10-29-2018

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_NODE_IS_TRANSMIT
C_LANES
C_LMFC_BUFFER_SIZE
Transceiver
SupportLevel
USE_RPAT
USE_JSPAT
TransceiverControl
C_SYSREF_SAMPLING_EDGE
C_PLL_SELECTION
AXICLK_FREQ
Fixed clocks (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs GTHE4_CHANNEL Speedfile Status
xczu9eg ffvb1156 -1 GTHE4_rx_1lane 0 1 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 1321 1171 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_rx_2lane 0 2 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 2284 1933 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_rx_3lane 0 3 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 3155 2695 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_rx_4lane 0 4 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4068 3456 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_rx_5lane 0 5 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 4963 4218 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_rx_6lane 0 6 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 5719 4979 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_rx_7lane 0 7 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 6579 5740 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_rx_8lane 0 8 1024 0 0 100 rx_core_clk=200 s_axi_aclk=100 7516 6501 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_tx_1lane 1 1 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1290 921 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_tx_2lane 1 2 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1510 1172 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_tx_3lane 1 3 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1739 1423 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_tx_4lane 1 4 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 1974 1674 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_tx_5lane 1 5 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2207 1925 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_tx_6lane 1 6 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2442 2176 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_tx_7lane 1 7 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2681 2427 0 0 0 0 PRODUCTION 1.23 10-29-2018
xczu9eg ffvb1156 -1 GTHE4_tx_8lane 1 8 GTHE4 0 false false false 0 0 100 s_axi_aclk=100 tx_core_clk=200 2918 2678 0 0 0 0 PRODUCTION 1.23 10-29-2018

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