Performance and Resource Utilization for Mailbox v2.1

Vivado Design Suite Release 2020.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Artix-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
C_ASYNC_CLKS
C_IMPL_STYLE
C_INTERCONNECT_PORT_0
C_INTERCONNECT_PORT_1
C_MAILBOX_DEPTH
C_READ_CLOCK_PERIOD_0
C_READ_CLOCK_PERIOD_1
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7a200t fbg676 -3 Configuration 01 0 0 2 2 16 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 255 201 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 02 0 0 2 2 64 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 336 225 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 03 0 0 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 3796 410 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 04 0 1 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 340 367 0 4 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 05 0 0 2 4 16 M1_AXIS_ACLK S0_AXI_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 162 113 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 06 0 0 4 4 16 M0_AXIS_ACLK M1_AXIS_ACLK S0_AXIS_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 50 15 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 07 1 0 2 2 16 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 320 440 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 08 1 0 2 2 64 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 413 532 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 09 1 0 2 2 256 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 756 624 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 10 1 1 2 2 2048 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 390 698 0 4 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 11 1 0 2 4 16 10000 10000 M1_AXIS_ACLK=100 S0_AXI_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 205 301 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 12 1 0 4 4 16 10000 10000 M0_AXIS_ACLK=100 M1_AXIS_ACLK=100 S0_AXIS_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 90 166 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Default S0_AXI_ACLK S1_AXI_ACLK=369 S0_AXI_ACLK 369 269 201 0 0 0 PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
C_ASYNC_CLKS
C_IMPL_STYLE
C_INTERCONNECT_PORT_0
C_INTERCONNECT_PORT_1
C_MAILBOX_DEPTH
C_READ_CLOCK_PERIOD_0
C_READ_CLOCK_PERIOD_1
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t ffg900 -3 Configuration 01 0 0 2 2 16 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 255 201 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 02 0 0 2 2 64 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 335 225 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 03 0 0 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 3795 410 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 04 0 1 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 339 367 0 4 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 05 0 0 2 4 16 M1_AXIS_ACLK S0_AXI_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 161 113 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 06 0 0 4 4 16 M0_AXIS_ACLK M1_AXIS_ACLK S0_AXIS_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 50 15 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 07 1 0 2 2 16 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 320 440 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 08 1 0 2 2 64 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 412 532 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 09 1 0 2 2 256 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 757 624 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 10 1 1 2 2 2048 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 391 698 0 4 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 11 1 0 2 4 16 10000 10000 M1_AXIS_ACLK=100 S0_AXI_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 205 301 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 12 1 0 4 4 16 10000 10000 M0_AXIS_ACLK=100 M1_AXIS_ACLK=100 S0_AXIS_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 90 166 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Default S0_AXI_ACLK S1_AXI_ACLK=515 S0_AXI_ACLK 515 275 202 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
C_ASYNC_CLKS
C_IMPL_STYLE
C_INTERCONNECT_PORT_0
C_INTERCONNECT_PORT_1
C_MAILBOX_DEPTH
C_READ_CLOCK_PERIOD_0
C_READ_CLOCK_PERIOD_1
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku040 ffva1156 -3 Configuration 01 0 0 2 2 16 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 245 201 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 02 0 0 2 2 64 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 318 225 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 03 0 0 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 3511 391 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 04 0 1 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 331 367 0 4 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 05 0 0 2 4 16 M1_AXIS_ACLK S0_AXI_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 157 113 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 06 0 0 4 4 16 M0_AXIS_ACLK M1_AXIS_ACLK S0_AXIS_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 48 15 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 07 1 0 2 2 16 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 308 440 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 08 1 0 2 2 64 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 391 532 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 09 1 0 2 2 256 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 707 624 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 10 1 1 2 2 2048 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 391 698 0 4 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 11 1 0 2 4 16 10000 10000 M1_AXIS_ACLK=100 S0_AXI_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 199 301 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 12 1 0 4 4 16 10000 10000 M0_AXIS_ACLK=100 M1_AXIS_ACLK=100 S0_AXIS_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 90 166 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Default S0_AXI_ACLK S1_AXI_ACLK=686 S0_AXI_ACLK 686 269 202 0 0 0 PRODUCTION 1.25 12-04-2018

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
C_ASYNC_CLKS
C_IMPL_STYLE
C_INTERCONNECT_PORT_0
C_INTERCONNECT_PORT_1
C_MAILBOX_DEPTH
C_READ_CLOCK_PERIOD_0
C_READ_CLOCK_PERIOD_1
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1761 -3 Configuration 01 0 0 2 2 16 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 255 201 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 02 0 0 2 2 64 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 336 225 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 03 0 0 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 3795 410 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 04 0 1 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 340 367 0 4 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 05 0 0 2 4 16 M1_AXIS_ACLK S0_AXI_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 162 113 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 06 0 0 4 4 16 M0_AXIS_ACLK M1_AXIS_ACLK S0_AXIS_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 50 15 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 07 1 0 2 2 16 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 321 440 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 08 1 0 2 2 64 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 412 532 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 09 1 0 2 2 256 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 756 624 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 10 1 1 2 2 2048 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 391 698 0 4 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 11 1 0 2 4 16 10000 10000 M1_AXIS_ACLK=100 S0_AXI_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 205 301 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 12 1 0 4 4 16 10000 10000 M0_AXIS_ACLK=100 M1_AXIS_ACLK=100 S0_AXIS_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 90 166 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Default S0_AXI_ACLK S1_AXI_ACLK=519 S0_AXI_ACLK 519 273 202 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
C_ASYNC_CLKS
C_IMPL_STYLE
C_INTERCONNECT_PORT_0
C_INTERCONNECT_PORT_1
C_MAILBOX_DEPTH
C_READ_CLOCK_PERIOD_0
C_READ_CLOCK_PERIOD_1
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 -3 Configuration 01 0 0 2 2 16 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 246 201 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 02 0 0 2 2 64 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 318 225 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 03 0 0 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 3510 391 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 04 0 1 2 2 2048 S0_AXI_ACLK S1_AXI_ACLK=100 N/A NOT FOUND 331 367 0 4 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 05 0 0 2 4 16 M1_AXIS_ACLK S0_AXI_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 156 113 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 06 0 0 4 4 16 M0_AXIS_ACLK M1_AXIS_ACLK S0_AXIS_ACLK S1_AXIS_ACLK=100 N/A NOT FOUND 48 15 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 07 1 0 2 2 16 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 306 440 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 08 1 0 2 2 64 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 388 532 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 09 1 0 2 2 256 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 712 624 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 10 1 1 2 2 2048 10000 10000 S0_AXI_ACLK=100 S1_AXI_ACLK=100 N/A NOT FOUND 390 698 0 4 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 11 1 0 2 4 16 10000 10000 M1_AXIS_ACLK=100 S0_AXI_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 197 301 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 12 1 0 4 4 16 10000 10000 M0_AXIS_ACLK=100 M1_AXIS_ACLK=100 S0_AXIS_ACLK=100 S1_AXIS_ACLK=100 N/A NOT FOUND 90 166 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Default S0_AXI_ACLK S1_AXI_ACLK=655 S0_AXI_ACLK 655 262 201 0 0 0 PRODUCTION 1.27 12-04-2018

COPYRIGHT

Copyright 2020 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.