Resource Utilization for MicroBlaze Debug Module (MDM) v3.2

Vivado Design Suite Release 2019.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Artix-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7a200t fbg676 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 91 111 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 94 113 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 103 115 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 238 167 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 160 176 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 227 202 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 328 381 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 372 350 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 220 206 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 360 347 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 401 274 0 0 0 PRODUCTION 1.23 2018-06-13
xc7a200t fbg676 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1267 902 0 0 0 PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t ffg900 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 92 111 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 94 113 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 103 115 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 238 167 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 160 176 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 228 202 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 328 381 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 372 350 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 220 206 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 360 347 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 402 274 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1267 902 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku040 ffva1156 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 86 111 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 90 113 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 100 115 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 237 169 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 158 176 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 224 202 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 323 381 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 366 350 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 214 206 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 393 347 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 396 274 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1258 902 0 0 0 PRODUCTION 1.25 12-04-2018

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1761 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 92 111 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 94 113 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 103 115 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 238 167 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 160 176 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 226 202 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 328 381 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 372 350 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 219 206 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 360 347 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 402 274 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1761 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1272 902 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_MB_DBG_PORTS
C_USE_UART
C_DBG_REG_ACCESS
C_DBG_MEM_ACCESS
C_USE_CROSS_TRIGGER
C_TRACE_OUTPUT
C_TRACE_CLK_OUT_PHASE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 -3 Configuration 01 1 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 88 111 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 02 2 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 90 113 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 03 4 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 100 115 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 04 32 0 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 237 169 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 05 1 1 0 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 158 176 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 06 1 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 221 202 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 07 1 0 0 1 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 323 381 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 08 1 0 0 0 0 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 TRACE_CLK=100 364 350 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 09 1 0 0 0 0 2 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXIS_ACLK=100 214 206 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 10 1 0 0 0 0 3 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 393 347 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 11 1 0 1 0 0 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 S_AXI_ACLK=100 397 274 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 Configuration 12 4 1 1 1 1 0 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK=30 DUT/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE=30 M_AXI_ACLK=100 S_AXI_ACLK=100 1260 902 0 0 0 PRODUCTION 1.27 12-04-2018

COPYRIGHT

Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.