Resource Utilization for VIO (Virtual Input/Output) v3.0

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

qvirtex7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_PROBE_OUT15_INIT_VAL
C_PROBE_OUT14_INIT_VAL
C_PROBE_OUT13_INIT_VAL
C_PROBE_OUT12_INIT_VAL
C_PROBE_OUT11_INIT_VAL
C_PROBE_OUT10_INIT_VAL
C_PROBE_OUT9_INIT_VAL
C_PROBE_OUT8_INIT_VAL
C_PROBE_OUT7_INIT_VAL
C_PROBE_OUT6_INIT_VAL
C_PROBE_OUT5_INIT_VAL
C_PROBE_OUT4_INIT_VAL
C_PROBE_OUT3_INIT_VAL
C_PROBE_OUT2_INIT_VAL
C_PROBE_OUT1_INIT_VAL
C_PROBE_OUT0_INIT_VAL
C_PROBE_OUT15_WIDTH
C_PROBE_OUT14_WIDTH
C_PROBE_OUT13_WIDTH
C_PROBE_OUT12_WIDTH
C_PROBE_OUT11_WIDTH
C_PROBE_OUT10_WIDTH
C_PROBE_OUT9_WIDTH
C_PROBE_OUT8_WIDTH
C_PROBE_OUT7_WIDTH
C_PROBE_OUT6_WIDTH
C_PROBE_OUT5_WIDTH
C_PROBE_OUT4_WIDTH
C_PROBE_OUT3_WIDTH
C_PROBE_OUT2_WIDTH
C_PROBE_OUT1_WIDTH
C_PROBE_OUT0_WIDTH
C_PROBE_IN8_WIDTH
C_PROBE_IN7_WIDTH
C_PROBE_IN6_WIDTH
C_PROBE_IN5_WIDTH
C_PROBE_IN4_WIDTH
C_PROBE_IN3_WIDTH
C_PROBE_IN2_WIDTH
C_PROBE_IN1_WIDTH
C_PROBE_IN0_WIDTH
C_EN_SYNCHRONIZATION
C_NUM_PROBE_OUT
C_EN_PROBE_IN_ACTIVITY
C_NUM_PROBE_IN
Fixed clocks (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xq7vx330t rf1157 -1I char_vio_v3_0_1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 16 0 9 clk=100 155 511 0 0 0 PRODUCTION 1.08 2015-10-01

Zynq-7000

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_PROBE_OUT15_INIT_VAL
C_PROBE_OUT14_INIT_VAL
C_PROBE_OUT13_INIT_VAL
C_PROBE_OUT12_INIT_VAL
C_PROBE_OUT11_INIT_VAL
C_PROBE_OUT10_INIT_VAL
C_PROBE_OUT9_INIT_VAL
C_PROBE_OUT8_INIT_VAL
C_PROBE_OUT7_INIT_VAL
C_PROBE_OUT6_INIT_VAL
C_PROBE_OUT5_INIT_VAL
C_PROBE_OUT4_INIT_VAL
C_PROBE_OUT3_INIT_VAL
C_PROBE_OUT2_INIT_VAL
C_PROBE_OUT1_INIT_VAL
C_PROBE_OUT0_INIT_VAL
C_PROBE_OUT15_WIDTH
C_PROBE_OUT14_WIDTH
C_PROBE_OUT13_WIDTH
C_PROBE_OUT12_WIDTH
C_PROBE_OUT11_WIDTH
C_PROBE_OUT10_WIDTH
C_PROBE_OUT9_WIDTH
C_PROBE_OUT8_WIDTH
C_PROBE_OUT7_WIDTH
C_PROBE_OUT6_WIDTH
C_PROBE_OUT5_WIDTH
C_PROBE_OUT4_WIDTH
C_PROBE_OUT3_WIDTH
C_PROBE_OUT2_WIDTH
C_PROBE_OUT1_WIDTH
C_PROBE_OUT0_WIDTH
C_PROBE_IN8_WIDTH
C_PROBE_IN7_WIDTH
C_PROBE_IN6_WIDTH
C_PROBE_IN5_WIDTH
C_PROBE_IN4_WIDTH
C_PROBE_IN3_WIDTH
C_PROBE_IN2_WIDTH
C_PROBE_IN1_WIDTH
C_PROBE_IN0_WIDTH
C_EN_SYNCHRONIZATION
C_NUM_PROBE_OUT
C_EN_PROBE_IN_ACTIVITY
C_NUM_PROBE_IN
Fixed clocks (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7z010 clg225 -3 char_vio_v3_0_2 clk=100 100 242 0 0 0 PRODUCTION 1.11 2014-09-11

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