Resource Utilization for DMA/Bridge Subsystem for PCI Express (PCIe) v4.1

Vivado Design Suite Release 2019.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
axi_data_width
en_axi_slave_if
en_axi_master_if
xdma_rnum_chnl
xdma_wnum_chnl
xdma_axi_intf_mm
c_m_axi_num_write
c_s_axi_num_write
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffva2104 -3 xcvu095g1x1_chnl1_mm X1 2.5_GT/s 1 1 AXI_Memory_Mapped axi_aclk=62 sys_clk=100 sys_clk_gt=100 10734 12179 0 12 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -3 xcvu095g1x1_chnl1_stream X1 2.5_GT/s 1 1 AXI_Stream axi_aclk=62 sys_clk=100 sys_clk_gt=100 9599 10830 0 12 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -3 xcvu095g1x1_chnl4_mm X1 2.5_GT/s 4 4 AXI_Memory_Mapped axi_aclk=62 sys_clk=100 sys_clk_gt=100 25403 27567 0 18 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -3 xcvu095g1x1_chnl4_stream X1 2.5_GT/s 4 4 AXI_Stream axi_aclk=62 sys_clk=100 sys_clk_gt=100 25196 25591 0 18 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -3 xcvu095g3x8_chnl1_mm X8 8.0_GT/s 1 1 AXI_Memory_Mapped axi_aclk=250 sys_clk=100 sys_clk_gt=100 20441 20264 0 31 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -3 xcvu095g3x8_chnl1_stream X8 8.0_GT/s 1 1 AXI_Stream axi_aclk=250 sys_clk=100 sys_clk_gt=100 18277 18933 0 31 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -3 xcvu095g3x8_chnl4_mm X8 8.0_GT/s 4 4 AXI_Memory_Mapped axi_aclk=250 sys_clk=100 sys_clk_gt=100 35825 35694 0 55 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -3 xcvu095g3x8_chnl4_stream X8 8.0_GT/s 4 4 AXI_Stream axi_aclk=250 sys_clk=100 sys_clk_gt=100 40066 37525 0 55 12 PRODUCTION 1.26 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
axi_data_width
en_axi_slave_if
en_axi_master_if
xdma_rnum_chnl
xdma_wnum_chnl
xdma_axi_intf_mm
c_m_axi_num_write
c_s_axi_num_write
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_16_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true 16 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 43389 45939 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_16_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true 16 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46800 50359 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_32_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true 32 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 44592 47068 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_32_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true 32 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 48204 51492 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 42561 45281 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46121 49693 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 42561 45281 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46121 49693 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_S_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 42561 45281 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_S_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46121 49693 0 64 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl1_mm X16 8.0_GT/s 512_bit 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 55330 53869 0 76 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl1_stream X16 8.0_GT/s 512_bit 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 51421 52615 0 76 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl2_mm X16 8.0_GT/s 512_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 60863 59018 0 92 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl2_stream X16 8.0_GT/s 512_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 61134 60528 0 92 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl4_mm X16 8.0_GT/s 512_bit 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 70864 69430 0 124 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl4_stream X16 8.0_GT/s 512_bit 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 81425 76343 0 124 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl1_mm X1 2.5_GT/s 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 11478 14882 0 31 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl1_stream X1 2.5_GT/s 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10419 13552 0 31 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl4_mm X1 2.5_GT/s 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 26388 30226 0 37 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl4_stream X1 2.5_GT/s 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 26114 28250 0 37 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X1 2.5_GT/s DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 7308 9995 0 29 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 2.5_GT/s DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 9264 13594 0 29 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X1 8.0_GT/s 64_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 7388 10116 0 29 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 8.0_GT/s 64_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 9304 13708 0 29 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X1 8.0_GT/s 64_bit true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 7388 10116 0 29 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 8.0_GT/s 64_bit true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 9304 13708 0 29 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl1_mm X1 8.0_GT/s 64_bit 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 11548 15002 0 31 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl1_stream X1 8.0_GT/s 64_bit 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 10536 13674 0 31 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl2_mm X1 8.0_GT/s 64_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 16486 20044 0 33 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl2_stream X1 8.0_GT/s 64_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 15623 18530 0 33 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl4_mm X1 8.0_GT/s 64_bit 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 26355 30342 0 37 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl4_stream X1 8.0_GT/s 64_bit 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 26156 28366 0 37 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_ep_S_8_bridge AXI_Bridge PCI_Express_Endpoint_device X1 8.0_GT/s 64_bit true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 7388 10116 0 29 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_rp_S_8_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 8.0_GT/s 64_bit true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 9304 13708 0 29 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X4 8.0_GT/s 128_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10197 13955 0 34 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X4 8.0_GT/s 128_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 12304 17618 0 34 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X4 8.0_GT/s 128_bit true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10197 13955 0 34 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X4 8.0_GT/s 128_bit true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 12304 17618 0 34 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_S_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X4 8.0_GT/s 128_bit true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10197 13955 0 34 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_S_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X4 8.0_GT/s 128_bit true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 12304 17618 0 34 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl1_mm X4 8.0_GT/s 128_bit 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 15197 19314 0 38 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl1_stream X4 8.0_GT/s 128_bit 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 13961 17984 0 38 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl2_mm X4 8.0_GT/s 128_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 20127 24401 0 42 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl2_stream X4 8.0_GT/s 128_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 19369 23308 0 42 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl4_mm X4 8.0_GT/s 128_bit 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 29985 34704 0 50 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl4_stream X4 8.0_GT/s 128_bit 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 31252 33999 0 50 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X8 8.0_GT/s 256_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 16668 20334 0 44 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X8 8.0_GT/s 256_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 19039 24171 0 44 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X8 8.0_GT/s 256_bit true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 16668 20334 0 44 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X8 8.0_GT/s 256_bit true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 19039 24171 0 44 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_S_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X8 8.0_GT/s 256_bit true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 16668 20334 0 44 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_S_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X8 8.0_GT/s 256_bit true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 19039 24171 0 44 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl1_mm X8 8.0_GT/s 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 24178 26621 0 50 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl1_stream X8 8.0_GT/s 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 21918 25285 0 50 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl2_mm X8 8.0_GT/s 256_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 29111 31719 0 58 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl2_stream X8 8.0_GT/s 256_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 28773 31463 0 58 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl4_mm X8 8.0_GT/s 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 39433 42040 0 74 0 PRODUCTION 1.26 08-13-2019
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl4_stream X8 8.0_GT/s 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 43399 43865 0 74 0 PRODUCTION 1.26 08-13-2019

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