説明

In timing simulation, the following errors occur:

"# ERROR: tstpbloc.tf(45): Illegal output port connection (1st connection).

# Region: /test_pb_loc_top/dut

# WARNING: tstpbloc.tf(45): [PCDPC] - Port size does not match connection size (6th connection).

# Region: /test_pb_loc_top/dut

# WARNING: tstpbloc.tf(45): [PCDPC] - Port size does not match connection size (7th connection)."

ソリューション

These errors occur when the testbench uses positional mapping instead of named mapping to instantiate the Design Under Test (DUT). The back-annotated netlist does not contain the signals in the same order in which they were declared in the pre-synthesis design. As a result, these errors appear when the simulator is unable to map the signals properly between the testbench and the DUT. Use named mapping to instantiate the DUT. Examples of named mapping are as follows:

VHDL

DUT: instance_name port map ( Clock => TB_Clock,

Input1 => TB_Input1,

...

OutputLast => TB_OutputLast );

Verilog

instance_name DUT (.Clock(TB_Clock),

.Input1(TB_Input1),

....

.OutputLast(TB_OutputLast) );