VHDL の場合 library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.vcomponents.all; library synplify; use synplify.attributes.all;
entity RAMB4_S8_synp is generic (INIT_00, INIT_01 : string := "0000000000000000000000000000000000000000000000000000000000000000"); port (WE, EN, RST, CLK : in std_logic; ADDR : in std_logic_vector(8 downto 0); DI : in std_logic_vector(7 downto 0); DO : out std_logic_vector(7 downto 0)); end RAMB4_S8_synp;
architecture XILINX of RAMB4_S8_synp is
component RAMB4_S8 port (WE, EN, RST, CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(8 downto 0); DI: in STD_LOGIC_VECTOR(7 downto 0); DO: out STD_LOGIC_VECTOR(7 downto 0)); end component; attribute xc_props of u1 : label is "INIT_00=" & INIT_00 & ",INIT_01=" & INIT_01;
begin
U1 : RAMB4_S8 port map (WE => WE, EN => EN, RST => RST, CLK => CLK, ADDR => ADDR, DI => DI, DO => DO);
end XILINX;
library IEEE; use IEEE.std_logic_1164.all;
entity block_ram_ex is port (CLK, WE : in std_logic; ADDR : in std_logic_vector(8 downto 0); DIN : in std_logic_vector(7 downto 0); DOUT : out std_logic_vector(7 downto 0)); end block_ram_ex;
architecture XILINX of block_ram_ex is
component RAMB4_S8_synp generic( INIT_00, INIT_01 : string := "0000000000000000000000000000000000000000000000000000000000000000"); port (WE, EN, RST, CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(8 downto 0); DI: in STD_LOGIC_VECTOR(7 downto 0); DO: out STD_LOGIC_VECTOR(7 downto 0)); end component;
begin
U1 : RAMB4_S8_synp generic map ( INIT_00 => "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF", INIT_01 => "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210") port map (WE => WE, EN => '1', RST => '0', CLK => CLK, ADDR => ADDR, DI => DIN, DO => DOUT);