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AR# 21439

LogiCORE SPI-4.2 (POS-PHY L4) - SPI-4.2 コアでマップを実行すると、警告および情報メッセージがいくつか表示される

説明

ISE デザイン ツールで SPI-4.2 デザインを実行すると、マップで警告および情報メッセージがいくつか表示されます。

これらのメッセージはどのように処理すればよいのですか。

ソリューション

警告メッセージ

"WARNING:LIT:222 - The use of IBUFDS_DIFF_OUT symbol "pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/data_ibuf0" (output signal=pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/_n0543) is only recommended for expert users."

IBUFDS_DIFF_OUT は Sink コアで使用されています。 このメッセージを無視しても問題はありません。

"WARNING:LIT:243 - Logical network pl4_v72_dyn_128_pl4_snk_top0/U0/cal0/r00/SPO has no load."

"WARNING:LIT:374 - The above warning message base_net_load_rule is repeated 68 more times for the following (max. 5 shown):

pl4_v72_dyn_128_pl4_snk_top0/U0/cal0/r01/SPO,

pl4_v72_dyn_128_pl4_snk_top0/U0/cal0/r02/SPO,

pl4_v72_dyn_128_pl4_snk_top0/U0/cal0/r03/SPO,

pl4_v72_dyn_128_pl4_snk_top0/U0/cal0/r04/SPO,

pl4_v72_dyn_128_pl4_snk_top0/U0/cal0/r05/SPO

To see the details of these warning messages, please use the -detail switch."

書き込み専用に使用されているブロック RAM ポートでは、出力が未接続のままになります。このメッセージを無視しても問題はありません。

"WARNING:LIT:381 - Attribute FACTORY_JF should be set to F0F0 for DCM_ADV symbol "pl4_src_clk0/tsclk_dcm0" (output signal=pl4_src_clk0/TSClk_dcmo) when attribute DLL_FREQUENCY_MODE is set to LOW."

スレーブ クロック モードの Source コアを生成したときにこのメッセージが表示されます。詳細は、(ザイリンクス アンサー 21441) を参照してください。

"WARNING:Pack:1566 - The LUT-1 inverter pl4_v72_dyn_128_pl4_src_top0/U0/core0/fifo0/FifoAlmostFull_n1_INV_0 failed to join the OLOGIC comp matched to output buffer SrcFFAlmostFull_n_OBUF. This may result in suboptimal timing. The LUT 1 inverter pl4_v72_dyn_128_pl4_src_top0/U0/core0/fifo0/FifoAlmostFull_n1_INV_0 drives multiple loads."

SPI-4.2 コアの機能には影響しません。このメッセージを無視しても問題はありません。

"WARNING:Pack:1185 - One or more I/O components have an illegal combination of property values. For each occurrence, the system will choose sensible defaults. To view each occurrence, create a detailed map report (run map using the -detail option)."

"WARNING:PhysDesignRules:812 - Dangling pin < SHIFTOUT2 > on block:< pl4_v72_dyn_128_pl4_src_top0/U0/io0/one_bit11/U1/pl4_v72_dyn_128_pl4_src_top0/U0/io0/one_bit11/U1>:< OSERDES_OSERDES >."

"WARNING:PhysDesignRules:812 - Dangling pin < SHIFTOUT1 > on block:< pl4_v72_dyn_128_pl4_src_top0/U0/io0/one_bit11/U1/pl4_v72_dyn_128_pl4_src_top0/U0/io0/one_bit11/U1 >:< OSERDES_OSERDES >."

"WARNING:PhysDesignRules:812 - Dangling pin < SHIFTIN1 > on block:< pl4_v72_dyn_128_pl4_src_top0/U0/io0/one_bit11/U1/pl4_v72_dyn_128_pl4_src_top0/U0/io0/one_bit11/U1 >:< OSERDES_OSERDES >."

"WARNING:PhysDesignRules:812 - Dangling pin < SHIFTIN2 > on block:< pl4_v72_dyn_128_pl4_src_top0/U0/io0/one_bit11/U1/pl4_v72_dyn_128_pl4_src_top0/U0/io0/one_bit11/U1 >:< OSERDES_OSERDES >."

すべての OSERDE に対し、SHIFTOUT1 および SHIFTOUT2 は未接続、SHIFTIN1 および SHIFTIN2 は Low (0) に設定されています。 このメッセージを無視しても問題はありません。

"WARNING:PhysDesignRules:1325 - Dangling pins on block:< U0/io0/dpa2/dpa_top0/CTLPAIR/SLAVE/U0/io0/dpa2/dpa_top0/CTLPAIR/SLAVE >:< ISERDES_ISERDES >. Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored. => They are on CE2 inputs not on the SHIFT1 and SHIFT2."

"WARNING:PhysDesignRules:812 - Dangling pin < TFB > on block:< pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/ctlslave/pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/ctlslave >:< ISERDES_ISERDES >."

"WARNING:PhysDesignRules:812 - Dangling pin < Q5 > on block:< pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster4/pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster4 >:< ISERDES_ISERDES>."

"WARNING:PhysDesignRules:812 - Dangling pin < OFB > on block:< pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster4/pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster4 >:< ISERDES_ISERDES>."

"WARNING:PhysDesignRules:812 - Dangling pin < O > on block:< pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster4/pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster4 >:< ISERDES_ISERDES >."

"WARNING:PhysDesignRules:812 - Dangling pin < TFB > on block:< pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster5/pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster5 >:< ISERDES_ISERDES >."

"WARNING:PhysDesignRules:812 - Dangling pin < SHIFTOUT2 > on block:< pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster5/pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster5 >:< ISERDES_ISERDES >."

"WARNING:PhysDesignRules:812 - Dangling pin < SHIFTOUT1 > on block:< pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster5/pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster5 >:< ISERDES_ISERDES >."

"WARNING:PhysDesignRules:812 - Dangling pin < SHIFTIN2 > on block:< pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster5/pl4_v72_dyn_128_pl4_snk_top0/U0/io0/dpa0/datamaster5 >:< ISERDES_ISERDES >."

ISERDES に対し、TFB および OFB、SHIFTOUT1 および 2 も接続されておらず、SHIFTIN1 および 2 は Low に接続、Q5 および Q6 は接続されていません。このメッセージを無視しても問題はありません。

情報メッセージ

"INFO:Map:91 - pl4_snk_credit_data_mux_128 symbol

"pl4_v72_dyn_128_pl4_snk_top0/U0/core0/queue0/aligner0/data_mux9" has an RLOCattribute and will be ignored since it is on a hierarchical block notdirectly recognized by map. This may be caused by an error in the Xilinxlibrary expansion for the symbol or by a third-party vendor incorrectlyexpanding the symbol."

"INFO:Map:91 - pl4_snk_credit_data_mux_128 symbol"pl4_v72_dyn_128_pl4_snk_top0/U0/core0/queue0/aligner0/data_mux8" has an RLOCattribute and will be ignored since it is on a hierarchical block notdirectly recognized by map. This may be caused by an error in the Xilinxlibrary expansion for the symbol or by a third-party vendor incorrectlyexpanding the symbol."

"INFO:Map:91 - pl4_snk_credit_data_mux_128 symbol"pl4_v72_dyn_128_pl4_snk_top0/U0/core0/queue0/aligner0/data_mux7" has an RLOCattribute and will be ignored since it is on a hierarchical block notdirectly recognized by map. This may be caused by an error in the Xilinxlibrary expansion for the symbol or by a third-party vendor incorrectlyexpanding the symbol."

上記のメッセージは複数回表示されることがあります。これは、SPI-4.2 コアにある未使用の RLOC 属性が原因で表示されます。このメッセージを無視しても問題はありません。

"INFO:MapLib:562 - No environment variables are currently set."

"INFO:LIT:244 - All of the single ended outputs in this design are using slewrate limited output drivers. The delay on speed critical single ended outputscan be dramatically reduced by designating them as fast outputs in theschematic."

AR# 21439
日付 12/15/2012
ステータス アクティブ
種類 一般
IP
  • SPI-4 Phase 2 Interface Solutions
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