AR# 32981: 11.2 XST - "ERROR:HDLCompiler:377 - "<file>.vhd" Line xx: Entity port in_port does not match with type std_logic_vector of component port"
AR# 32981
11.2 XST - 「ERROR:HDLCompiler:377 - "<file>.vhd" Line xx: Entity port in_port does not match with type std_logic_vector of component port」というエラー メッセージが表示される
ERROR:HDLCompiler:377 - "<file>.vhd" Line xx: Entity port in_port does not match with type std_logic_vector of component port "<file>.vhd" Line xx: in_port is declared here
コード例 :
library ieee; use ieee.std_logic_1164.all;
entity subb_0014 is port(in_port : in bit_vector(3 downto 0); out_port: out bit_vector(3 downto 0)); end subb_0014;
architecture beh of subb_0014 is begin out_port <= in_port; end;
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library ieee; use ieee.std_logic_1164.all;
entity ex_0014 is port(in_port : in std_logic_vector(3 downto 0); out_port: out std_logic_vector(3 downto 0)); end ex_0014;
architecture beh of ex_0014 is
component subb_0014 is port(in_port : in std_logic_vector(3 downto 0); out_port: out std_logic_vector(3 downto 0)); end component;
begin inst : subb_0014 port map(in_port => in_port, out_port=>out_port); end;
entity subb_0014 is port(in_port : in std_logic_vector(3 downto 0); -- Note: Info points here out_port: out std_logic_vector(3 downto 0)); -- Note: Info points here end subb_0014;
architecture beh of subb_0014 is begin out_port <= in_port; end;
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library ieee; use ieee.std_logic_1164.all;
entity ex_0014 is port(in_port : in std_logic_vector(3 downto 0); out_port: out std_logic_vector(3 downto 0)); end ex_0014;
architecture beh of ex_0014 is
component subb_0014 is port(in_port : in std_logic_vector(3 downto 0); -- Note: Error points here out_port: out std_logic_vector(3 downto 0)); -- Note: Error points here end component;
begin inst : subb_0014 port map(in_port => in_port, out_port=>out_port); end;