AR# 32984: 11.x XST - "ERROR:HDLCompiler:16 - "<file>.vhd" Line xx : <width> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components."
AR# 32984
11.x XST - 「ERROR:HDLCompiler:16 - "<file>.vhd" Line xx : <width> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components.」というエラー メッセージが表示される
ERROR:HDLCompiler:16 - "<file>.vhd" Line xx: <width> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components.
コード例 :
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity ex_0018 is port(in_port : in std_logic_vector(7 downto 0); out_port: out std_logic_vector(7 downto 0)); end ex_0018;
architecture beh of ex_0018 is
procedure add_0018 ( constant width: integer:=8; -- Note: Error point here signal inp: in std_logic_vector(width-1 downto 0); signal outp: out std_logic_vector(width-1 downto 0)) is begin outp <= inp + 5; end add_0018;
begin add_0018(inp=>in_port, outp=>out_port); end;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity ex_0018 is port(in_port : in std_logic_vector(7 downto 0); out_port: out std_logic_vector(7 downto 0)); end ex_0018;
architecture beh of ex_0018 is constant width: integer:=8;
procedure add_0018 ( signal inp: in std_logic_vector(width-1 downto 0); signal outp: out std_logic_vector(width-1 downto 0)) is begin outp <= inp + 5; end add_0018;
begin add_0018(inp=>in_port, outp=>out_port); end;