AR# 40491: 13.1 CORE Generator - I receive "coreutil:648" errors when I attempt to open a project with Virtex-6 PCIe Block with location set to X0Y0&X0Y1
"ERROR:coreutil:648 - Unable to create design from file '[project path]/coregen.cgc' ERROR:coreutil:648 - Unable to create design from file '[project path]' ERROR:sim:722 - Unable to open project '[project path]/coregen.cgc' ERROR:encore:268 - Project [project path]/coregen.cgc could not be opened"