UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40841

SPI-4.2 v11.1 - SPI-4.2 デザインを NGDBuild、MAP、PAR、BitGen までインプリメントすると警告メッセージが表示される

説明

SPI-4.2 デザインを NGDBuild、MAP、PAR、BitGen までインプリメントすると警告メッセージが表示されます。

ソリューション


これらの警告メッセージは無視しても問題ありません。

NGDBuild :
WARNING:NgdBuild:1440 - User specified non-default attribute value (2.85) was detected for the CLKIN1_PERIOD attribute on MMCM "pl4_snk_clk0/mmcm0".Thisdoes not match the PERIOD constraint value (350 MHz.). The uncertaintycalculation will use the PERIOD constraint value. This could result inincorrect uncertainty calculated for MMCM output clocks.
(this one above can occur for multiple clocks, depending on which ones use MMCMs)

WARNING:NgdBuild:440 - FF primitive 'core_pl4_src_top0/U0/core0/data0/u10/dip4_val/FF5' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive 'core_pl4_src_top0/U0/rst0/rstu1/fifo_reset_ff' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive'core_pl4_src_top0/U0/rst0/rstd/fifo_reset_ff' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive'core_pl4_src_top0/U0/rst0/rst1/fifo_reset_ff' has unconnected output pin

さらに、128 ビットのコアに対し NGDBuild で次のメッセージが複数回表示されます。
WARNING:NgdBuild:440 - FF primitive 'core_pl4_snk_top0/U0/Gen128.core0/queue0/aligner0/SLOT_MUX_GEN[6].ss2/one0.srl1[0].d3' has unconnected output pin

MAP :
WARNING:MapLib:701 - Signal AXI_SNK_AWADDR(1) connected to top level port AXI_SNK_AWADDR(1) has been removed.
WARNING:MapLib:701 - Signal AXI_SNK_AWADDR(0) connected to top level port AXI_SNK_AWADDR(0) has been removed.
WARNING:MapLib:701 - Signal AXI_SRC_AWADDR(1) connected to top level port AXI_SRC_AWADDR(1) has been removed.
WARNING:MapLib:701 - Signal AXI_SRC_AWADDR(0) connected to top level port AXI_SRC_AWADDR(0) has been removed.

PAR :
WARNING:Par:288 - The signal core_pl4_snk_top0/U0/Gen128.core0/queue0/RecFifoRdAddrGray<0> has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

さらに、スタティック アライメントに対し、PAR で次のメッセージが複数回表示されます。
WARNING:Par:288 - The signal core_pl4_snk_top0/U0/io0/StaticAlign.buffer_data/BUF_v7.BUFIN100.Dat100/OB has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SnkIdelayRefClk_bufg has no load. PAR will not attempt to route this signal.

DRC (スタティック アライメントのみ) :

WARNING:PhysDesignRules:367 - The signal <core_pl4_snk_top0/U0/io0/StaticAlign.buffer_data/BUF_v7.BUFIN30.Dat30/OB> isincomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal <SnkIdelayRefClk_bufg> is incomplete.The signal does not drive any load pins in the design.
AR# 40841
日付 12/15/2012
ステータス アクティブ
種類 一般
IP
  • SPI-4 Phase 2 Interface Solutions
このページをブックマークに追加