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AR# 45688

ChipScope IBERT, Virtex-6 GTX - RX Sampling point slider does not function with PLL_DIVSEL_OUT is set to 2 or 4


The following answer record provides details on the functionality of the RX sampling point slider in the Virtex-6 GTX IBERT core when the RX/TXPLL_DIVSEL_OUT is set to 2 or 4.


The IBERT core uses the PMA_CDR_SCAN attribute to offset the sampling point. Because of this, the RX sampling point slider in the IBERT core is only valid when the GT is set at the full rate (ie. PLL_DIVSEL_OUT = 1). If the PLL output dividers are set at 2 or 4, the RX sampling point slider will not function.

This is not bug with the core. It is a design limitation on how the slider works in the ChipScope IBERT core. If the RX sampling point slider needs to be used, select PLL settings that will set the line rate while the PLL_DIVSEL_OUT attribute is set to 1.

AR# 45688
日付 12/15/2012
ステータス アクティブ
種類 一般
  • Virtex-6 LXT
  • Virtex-6 CXT
  • Virtex-6 SXT
  • ChipScope Pro - 13.3
  • ChipScope Pro - 12.1
  • ChipScope Pro - 12.2
  • More
  • ChipScope Pro - 12.3
  • ChipScope Pro - 12.4
  • ChipScope Pro - 13.1
  • ChipScope Pro - 13.2
  • ChipScope Pro - 13.4
  • Less