説明

ソリューション

#include "xil_cache.h"
Xil_DCacheDisable();

for ( Index = 0; Index < CIP_AXI4_MASTER_SELFTEST_BUFSIZE; Index++ )
{
SrcBuffer[Index] = Index;
DstBuffer[Index] = 0;
}

xil_printf(" ******* flushing data cache!!! \n\r");
Xil_DCacheFlushRange((unsigned int)SrcBuffer, CIP_AXI4_MASTER_SELFTEST_BUFSIZE);
Xil_DCacheFlushRange((unsigned int)DstBuffer, CIP_AXI4_MASTER_SELFTEST_BUFSIZE);

xil_printf(" - start user logic master module to receive word from the source\n\r");

for ( Index = 0; Index < CIP_AXI4_MASTER_SELFTEST_BUFSIZE; Index++ )
{
SrcBuffer[Index] = Index;
DstBuffer[Index] = 0;
}

xil_printf(" ******* flushing data cache for source only!!! \n\r");
Xil_DCacheFlushRange((unsigned int)SrcBuffer, CIP_AXI4_MASTER_SELFTEST_BUFSIZE);
xil_printf(" - start user logic master module to receive word from the source\n\r");
/**** more code from selftest ****/

xil_printf(" ******* invalidate destination data cache to force correct read!!! \n\r");
Xil_DCacheInvalidateRange((unsigned int)DstBuffer, CIP_AXI4_MASTER_SELFTEST_BUFSIZE);
/*** do the memory compare as in the original code ***/