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  3. AR# 54550: LogiCORE IP MIPI D-PHY - Vivado 2015.3 およびそれ以降のバージョンのリリース ノートおよび既知の問題

AR# 54550

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LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions

説明

This answer record contains the Release Notes and Known Issues for the MIPI D-PHY Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

MIPI D-PHY LogiCORE IP Page:

https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html

ソリューション

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions:

  • Subsystem or IP - See the Change log included with the core in Vivado.
  • Subsystem or IP - Click on the Change log links below.
  • Standalone Software Drivers - See the Change log included with the Doxygen Drivers in the Xilinx SDK
  • Standalone Software Drivers - Github Software Driver Repo#

Please seek technical support via the Video Board of the Xilinx Community Forums.

The Xilinx Forums are a great resource for technical support.

The entire Xilinx User Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools VersionIP Change logIP Patches
v4.3 (Rev. 2)2021.1(Xilinx Answer 76541) 
v4.3 (Rev. 1)2020.3-TBA- 
v4.32020.2(Xilinx Answer 75786) 
v4.22020.1(Xilinx Answer 73626)(Xilinx Answer 75543)
v4.1 (Rev. 5)2019.2(Xilinx Answer 72923)(Xilinx Answer 73316)
v4.1 (Rev. 4)2019.1.1(Xilinx Answer 72494)(Xilinx Answer 72758)
v4.1 (Rev 3)2019.1(Xilinx Answer 72242) 
v4.1 (Rev. 2)2018.3(Xilinx Answer 71806) 
v4.1 (Rev. 1)2018.2(Xilinx Answer 71212) 
v4.12018.1(Xilinx Answer 70699) 
v4.0 (Rev. 1)2017.4(Xilinx Answer 70386)(Xilinx Answer 70530)
v4.02017.3(Xilinx Answer 69903)(Xilinx Answer 70195)
v3.1 (Rev.1)2017.2(Xilinx Answer 69326)(Xilinx Answer 69760)
v3.12017.1(Xilinx Answer 69055) 
v3.0 (Rev. 1)2016.4(Xilinx Answer 68369)(Xilinx Answer 68810)
v3.02016.3(Xilinx Answer 68021) 
v2.0 (Rev. 1)2016.2(Xilinx Answer 67345) 
v2.02016.1(Xilinx Answer 66930) 
v1.02015.3(Xilinx Answer 65570) 

General Guidance

The table below provides Answer Records for general guidance when using the MIPI D-PHY core.

Article NumberArticle Title
(Xilinx Answer 73209)The minimum value of Tskewcal (Skew-Calibration Timing Parameter) for MIPI D-PHY IP
(Xilinx Answer 72604)Where do I find SSN analysis data for the MIPI_DPHY_DCI @ 2.5Gb/s?
(Xilinx Answer 71582)MIPI D-PHY RX or MIPI CSI-2 RX Subsystem reporting packet corruption at higher line-rates
(Xilinx Answer 71205)When using MIPI D-PHY TX, can we assert/de-assert DL*_TXREQUESTHS / CL_TXREQUESTHS at the same time?
(Xilinx Answer 69530)How much margin is in the MIPI D-PHY RX line rate settings?
(Xilinx Answer 67249)What is the maximum value of start-up time before High-speed data transfer?

Known and Resolved Issues

The following table provides known issues for the MIPI D-PHY core, starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 76383)MIPI D-PHY TX has setup violations on paths within the IP with register interface enabled or timeout counters registers enabledv4.3 (Rev. 1)-
(Xilinx Answer 75852)MIPI D-PHY TX IP for Versal devices might have rising edge misalignment between clock and data outputs.v4.3 (Rev. 1)-
(Xilinx Answer 75574)MIPI D-PHY RX with resources optimization preset set to "CSI2RX_XLNX2" is not workingv4.2v4.3
(Xilinx Answer 73633)Why am I failing timing on some -1 parts when trying to set the line rate to 2500Mbps using Vivado 2019.2?v4.1 (Rev. 5)v4.1 (Rev. 5)
(Xilinx Answer 73188)IDELAYCTRL_RDY is not used in MIPI in FIXED modev4.1 (Rev. 4)v4.1 (Rev. 5)
(Xilinx Answer 71846)MIPI D-PHY TX with 600Mbps line-rate setting has output signal stuck after the first HS transmission.v4.1 (Rev. 1)v4.1 (Rev. 2)
(Xilinx Answer 69531)Why do I get the warning "ncelab: *dphy_ip/mipi_dphy.srcs/sources_1/ip/mipi_dphy_rx1/mipi_dphy_rx1_core.v,436|49): implicit wire has no fanin" on system_rst_in when simulating the MIPI DPHY RX?v3.1v4.0
(Xilinx Answer 70591)Can I change IDELAY tap values on the fly for MIPI D-PHY IP v4.0? (IP targeting 7 Series devices)v4.0v4.1
(Xilinx Answer 70581)Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devicesv4.0 (Rev. 1)v4.1
(Xilinx Answer 70196)On 7 Series Devices, High-Speed Lanes are unconnected in the synthesized design with Auto Calibration Auto and external IDELAYCTRLv4.0v4.0 (Rev. 1)
(Xilinx Answer 69671)When using 7 Series Devices to implement MIPI D-PHY TX, why do I see overshoot on the output signal during HS-->LP transmission?v3.1 (Rev. 1)v4.0
(Xilinx Answer 69931)When using MIPI D-PHY TX, why is the HS-PREPARE length violating MIPI D-PHY specification version 1.1?v3.1 (Rev. 1)v4.0 (Rev. 1)
(Xilinx Answer 69766)When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes when targeting 7 Series devices?v3.1 (Rev. 1)v4.0 (Rev. 1)
(Xilinx Answer 67365)What is the behavior of receiver IP on SoT pattern and why do I not see an error when sending "BC" and receiving "B8"?v2.0v3.0
(Xilinx Answer 69274)Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY Controller RX?v3.1v4.1
(Xilinx Answer 69057)Why is an SOTsynchs error generated from MIPI DPHY RX IP or MIPI CSI-2 RX Subsystem?v3.0 (Rev. )v3.1
(Xilinx Answer 68603)Slave Mode (Shared logic in example design) D-PHY RX IP does not work when it is sharing resources with Master mode (Shared Logic in core) D-PHY RX IPv3.0 (Rev .1)v3.1
(Xilinx Answer 68603)Why does the Slave IP not work after updating to 2016.4?v3.0 (Rev. 1)v3.1
(Xilinx Answer 67296)Are multi-lane use cases supported in MIPI D-PHY IP?v2.0v3.1
(Xilinx Answer 67258)Why is there a change to the rxvalidhs behavior when receiving in high-speed mode?v1.01.0v2.0

Revision History: 
06/30/2021Added IP version up to Vivado 2021.1
04/15/2021Added (Xilinx Answer 76383) to "Known and Resolved Issues" Table
03/05/2021

Added IP version up to Vivado 2020.3.
Added (Xilinx Answer 75852) to "Known and Resolved Issues" Table

09/10/2020

Added IP version up to Vivado 2020.2.

09/10/2020

Added IP version up to Vivado 2020.1.
Added (Xilinx Answer 75574) to "Known and Resolved Issues" Table

04/24/2020Added (Xilinx Answer 73633) to "Known and Resolved Issues" Table
02/04/2020Added IP patch (Xilinx Answer 73316) , Updated "Known and Resolved Issues" Table. Added (Xilinx Answer 73330)
12/23/2019Added General Guidance (Xilinx Answer 73209)
11/13/2019Added IP version up to Vivado 2019.2 to the Version Table
07/30/2019Added (Xilinx Answer 72604) to General Guidance Table and v4.1 (Rev. 4) to the revision table
06/21/2019Removed Xilinx Answer 66088
05/13/2019Added (Xilinx Answer 71846) and v4.1 (Rev 3) to revision table
01/18/2019Added (Xilinx Answer 71582) to general guidance and v4.1 (Rev. 1) and v4.1 (Rev. 2) to revision table
06/08/2018Added (Xilinx Answer 71205)
05/25/2018Added (Xilinx Answer 70530) to Version Table
04/13/2018Added (Xilinx Answer 69530) and (Xilinx Answer 69531)
04/04/2018Added v4.1 to Version Table (Xilinx Answer 70196), (Xilinx Answer 70581), and (Xilinx Answer 70591)
01/25/2018Added (Xilinx Answer 69274)
01/18/2018Added v4.0 (Rev. 1) to Version Table
11/03/2017Added (Xilinx Answer 69766), (Xilinx Answer 69671), (Xilinx Answer 69931), and (Xilinx Answer 69760)
10/23/2017Added v3.1 (Rev.1) and v4.0 to Version Table and (Xilinx Answer 67365)
06/05/2017Added (Xilinx Answer 69274)
04/05/2017Added v3.1 to Version Table, (Xilinx Answer 68810), and (Xilinx Answer 69057)
02/07/2017Added v2.0 (Rev.1), v3.0 and v3.0 (Rev.1) to Version Table and (Xilinx Answer 68603)
05/31/2016Added (Xilinx Answer 67258), (Xilinx Answer 67296), and (Xilinx Answer 67249)
04/06/2016Added v2.0 to Version Table
12/07/2015Added Xilinx Answer 66088
09/30/2015Initial Release

アンサー レコード リファレンス

マスター アンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
56852 ザイリンクス マルチメディア、ビデオ、および画像ソリューション センター - 主な問題 N/A N/A

サブアンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
67296 LogiCORE IP MIPI D-PHY Controller v2.0 - MIPI D-PHY IP でのマルチレーンのサポート N/A N/A
67249 LogiCORE IP MIPI D-PHY Controller - What is the maximum value of start-up time before High-speed data transfer? N/A N/A
67258 LogiCORE IP MIPI D-PHY v2.0 - 高速モードでの受信時に rxvalidhs の動作が変更される理由 N/A N/A
68603 LogiCORE IP MIPI D-PHY v3.0 (Rev. 1) – スレーブ モード (サンプル デザインの共有ロジック) の D-PHY RX IP が マスター モード (コアの共有ロジック) の D-PHY RX IP とリソースを共有すると機能しない N/A N/A
69057 LogiCORE IP MIPI D-PHY v3.0 (Rev. 1) - MIPI DPHY RX IP または MIPI CSI-2 RX Subsystem から SOTSynchs エラーが生成されるのはなぜか N/A N/A
69173 2017.1 LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) - LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) のパッチ アップデート N/A N/A
69250 LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) - 一部のライン レートの設定について MIPI トランスミッターのクロック/データが中央揃えの関係にならない N/A N/A
69274 LogiCORE IP MIPI D-PHY v3.1, v3.1 (Rev. 1) および v4.0 (Rev. 1) - MIPI D-PHY RX で ulpsactivenot が 1 クロック間しかアサートされない N/A N/A
69530 LogiCORE MIPI D-PHY および MIPI CSI-2 RX Subsystem - MIPI D-PHY RX ライン レートの設定にはどれくらいのマージンがあるか N/A N/A
67365 LogiCORE IP MIPI D-PHY v2.0 - SoT パターンのレシーバー IP の予期動作と、BC を送信し、B8 を受信するとエラーがない理由 N/A N/A
69931 LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) - MIPI D-PHY TX を使用すると HS-PREPARE の長さが MIPI D-PHY仕様 v1.1 に違反する N/A N/A
69766 LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) - MIPI D-PHY TX を使用すると、レーン間の SoT 信号にスキューが見られる N/A N/A
69671 LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) - 7 シリーズ デバイスを使用して MIPI D-PHY TX をインプリメントすると、HS から LP への伝送中に出力にオーバーシュートが見られる N/A N/A
69760 2017.2 MIPI D-PHY v3.1 (Rev. 1) - LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) のパッチ アップデート N/A N/A
70196 LogiCORE IP MIPI D-PHY v4.0 - 7 シリーズ デバイスでは自動キャリブレーションと外部 IDELAYCTRL を使用する合成デザインで高速レーンが未接続のままになる N/A N/A
70581 LogiCORE IP MIPI D-PHY Controller v4.0 (rev.1) (または MIPI CSI-2 Receiver Subsystem v3.0 (Rev. 1)) - UltraScale+ デバイスをターゲットにすると MIPI RX IP で SoT/ECC/CRC エラーが発生する N/A N/A
70591 LogiCORE IP MIPI D-PHY v4.0 - MIPI D-PHY IP v4.0 の IDEALY タップ値をオンザフライで変更可能か(7 シリーズ デバイスをターゲットにした IP) N/A N/A
70530 2017.4 LogiCORE IP MIPI D-PHY v4.0 (rev.1) - MIPI D-PHY LogiCORE IP v4.0 (rev.1) のパッチ アップデート N/A N/A
69531 LogiCORE MIPI D-PHY v3.1, MIPI CSI-2 Rx Subsystem v2.2 (Rev. 1) - MIPI DPHY RX をシミュレーションしていると「ncelab: *dphy_ip/mipi_dphy.srcs/sources_1/ip/mipi_dphy_rx1/mipi_dphy_rx1_core.v,436|49): implicit wire has no fanin'' on system_rst_in」という警告メッセージが表示される N/A N/A
71205 LogiCORE IP MIPI D-PHY v4.0 - MIPI D-PHY TX を使用すると、DL*_TXREQUESTHS / CL_TXREQUESTHS を同時にアサート/ディアサートできるか N/A N/A
71374 MIPI D-PHY - UltraScale+ デバイス - 同じバンクにある 2 つの IP インスタンスを同時にリセットする必要がある N/A N/A
71582 2018.2 LogiCORE IP MIPI D-PHY v4.1 (rev.1) MIPI CSI-2 RX Subsystem v3.0 (rev.3) - MIPI D-PHY RX または MIPI CSI-2 RX Subsystem でライン レートが高いときにパケット破損がレポートされる N/A N/A
73330 LogiCORE IP MIPI D-PHY v4.1 (rev.5) - 1500 Mbps ライン レート設定で IP が生成されると MIPI D-PHY TX INIT_DONE がアサートされない N/A N/A
73316 LogiCORE IP MIPI D-PHY v4.1 (Rev. 5) - MIPI D-PHY LogiCORE IP v4.1 (Rev. 5) 用のパッチ アップデート N/A N/A

関連アンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
65242 MIPI CSI-2 Receiver Subsystem - Vivado ツール 2015.3 バージョン以降のリリース ノートおよび既知の問題 N/A N/A
67896 MIPI CSI-2 Transmitter Subsystem - Vivado ツール 2016.3 バージョン以降のリリース ノート N/A N/A
AR# 54550
日付 06/29/2021
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