International Workshop on Reconfigurable Acceleration in Datacenters (ReconfigAccel 2018)

Date Venue
June 12, 2018

Beijing International Convention Center

No.8 Beichen Dong Road, Chaoyang District, Beijing China 100101


With the slowdown of general-purpose processor scaling due to dark silicon limitations, customized hardware accelerators like FPGAs, CGRAs, and ASICs have gained increased attention in modern datacenters due to their lower power, high performance low latency, and energy efficiency. Evidenced by Microsoft's FPGA deployment in its datacenters, FPGA-enabled public cloud announcements from Amazon, Alibaba, Baidu, Huawei and Tencent, as well as Google's TPU cloud deployment, integrating customized hardware accelerators into datacenters is considered one of the most promising approaches to sustain future datacenter growth.

Deploying hardware accelerators in datacenters is still in its early stage and there are many research challenges ahead. For example, what kind of applications and workloads benefit from accelerators, how to program and manage such accelerators in the datacenter, and how to model and optimize these acceleration architectures? In this workshop, we plan to bring together academic and industry experts to share their experience, discuss challenges they face as well as potential focus areas for the community. Below is the planed workshop content.

Workshop Topics

We solicit extended abstracts (1 – 2 pages) from the community and selected ones will be invited to give a 20 mins talk with 10 min Q/A for each talk. Below is the proposed list of topics for the workshop. Note that primary focus for this workshop will be the emerging area of customized hardware accelerators such as FPGAs, CGRAs, and ASICs; there is already well chronicled research focus of GPUs in the datacenter. Workshop topics include, but are not limited to:

  • Large-scale application characterization, optimization, and evaluation, which leverage hardware accelerators, e.g., for machine learning, big data analytics, genomics, and video transcoding
  • Programming models, compilers and debugging support to make it easier to program accelerators
  • Runtime and virtualization support to enable efficient deployment and scheduling of accelerators in datacenters
  • New acceleration architectures for datacenters, e.g., novel reconfigurable, programmable, low-power accelerator designs, near data acceleration architectures
  • Other research infrastructures (e.g., modeling/simulation/characterization) that enable the above studies

Organizing Chairs

Time Content Presenter
9:00 - 9:15 Opening Remark

Hugo A. Andrade
Director, Xilinx University Program

9:15 - 10:00 Keynote: Adaptable Computing – The Future of Acceleration with FPGAs

Dan Gibbons
Vice President, FPGA Software Development at Xilinx

10:00 - 10:15 Coffee Break
10:15 - 12:15

Session 1: Novel Accelerators and Architectures
Session Chair: Zhiru Zhang, Cornell University

10:15 - 10:45 Accelerating Fast Algorithms for CNNs on FPGAs

Yun (Eric) Liang
Assistant Professor, School of EECS, Peking University; Assistant Director, Center for Energy-efficient Computing and Applications (CECA)

10:45 - 11:15 Ultra-Low Latency and High Performance Deep Learning Accelerator Based on FPGA

Xulin Yu
Director of Heterogeneous Computing from Alibaba Infrastructure Service

11:15 - 11:45

Reconfigurable Architecture for Control-Intensive Kernels with Control Speculation and Triggered Instructions

Jianfeng Zhu
Postdoc, Institute of Microelectronics, Tsinghua University

11:45 - 12:15  The Case for Labeled Computer Architecture: A New Perspective on Software Defined Computer Architecture

Yungang Bao
Professor, Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS); Executive Director, Center of Advanced Computer Systems (ACS) of ICT

12:15 - 13:30 Lunch
13:30 - 15:00

Session 2: Tools and Infrastructures
Session Chair: Guojie Luo, Peking University

13:30 - 14:00 FPGAs at HyperScale – Where We’ve Been, and Where We’re Going

Andrew Putnam
Principal Research Hardware Design Engineer, Microsoft Research Technologies (MSR-T) lab; Founding Member, Microsoft Catapult Project

14:00 - 14:30 FPGA Compilation and Acceleration

Peter Han
General Manager, Falcon Computing Solutions, Inc. Beijing

14:30 - 15:00 Integrating AI into your Accelerated Cloud Applications

Rahul Nimaiyar
Director, Xilinx Machine Learning IP, Data Center IP Solutions

15:00 - 15:30 Coffee Break
15:30 - 17:30

Session 3: New Advances in Machine Learning
Session Chair: Yun (Eric) Liang, Peking University

15:30 - 16:00 Deep Neural Network Compression through Orthogonal Transforms

Zhiru Zhang
Assistant Professor, School of ECE, Cornell University; Co-founded AutoESL Design Technologies, Acquired by Xilinx in 2011 (now known as Vivado HLS)

16:00 - 16:30 Training on FPGA

Yu Wang
Associate Professor, E.E. Dept., Tsinghua University; Co-Founder, Deephi Tech

16:30 - 17:00 Towards Low-Precision Training: Dynamic Reconfigurable-Precision SGD on FPGAs

Guojie Luo
Associate Professor, School of EECS, Peking University; Executive Director, Center for Energy-efficient Computing and Applications (CECA)

17:00 - 17:30 TBD

Wei Qi

* The agenda is subject to change.