Overview

AMD Versal™ AI Engine Development using Vitis Model Composer

AMD Vitis™ Model Composer enables the rapid simulation, exploration, and code generation of algorithms targeted for Versal AI Engines from within the Simulink environment. You can achieve this by using the AI Engine library blocks or by importing kernels and data-flow graphs into Vitis Model Composer as blocks and controlling the behavior of the kernels and graphs by configuring the block GUI parameter. The tool also allows you to model and simulate a design with a mix of AI Engine and Programmable logic (HDL/HLS) blocks. Simulation results can be visualized by seamlessly connecting Simulink source and sink blocks with Vitis Model Composer AI Engine blocks. 

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AMD Vitis Simulink diagram
AMD Toolbox diagram

Vitis Model Composer provides a set of performance-optimized blocks for use within the Simulink environment. These include:

AI Engine blocks
  • Includes a set of complex AI Engine DSP building blocks related to FIR, FFT, DDS, and mixers.
  • Contains blocks to import kernels and graphs that can be targeted to the AI Engine portion of Versal devices.
HLS (Targeting PL and generates HLS code) 
  • Offers predefined blocks that include functional blocks for math, linear algebra, logic, and bit-wise operations
  • Block to import HLS kernels which can be targeted to the PL portion of Versal devices.
HDL (Targeting PL and generates RTL code)
  • Blocks to model logic, math, and DSP elements and synthesize them on an FPGA
  • Includes a FIR Compiler block that targets the dedicated DSP48E1, DSP48E2 hardware resources in Versal design
  • Blocks that support connection between the AI Engine and the AMD HDL blockset.

Videos

Design Examples

Explore Design Examples on how to use Vitis Model Composer Blocks
AI Engine Examples on Github
Programmable Logic (PL) + AI Engine Design Examples

Github Tutorials

Access Tutorials on AI Engine Library, HLS and HDL

HLS Library

These tutorials help you examine the Vitis Model Composer HLS library, build a simple design using HLS blocks, and learn about the data types supported by Vitis Model Composer.

View Tutorials

HDL Library

These tutorials show you how to use the Vitis Model Composer HDL library to specify a design in Simulink® and synthesize the design into an FPGA. 

View Tutorials

Resources

Vitis Model Composer GitHub Repository

Explore the Github repository to learn more about rapid design using Vitis Model Composer.

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脚注
  1. Based on testing on August 10, 2023, across 1000 Vitis L2/L3 code library designs, with Vitis HLS release 2023.2 vs. Vitis HLS 2023.1. System configuration during testing: Intel Xeon E5-2690 v4 @ 2.6GHz CPU, 256GB RAM, RedHat Enterprise Linux 8.6. Actual performance will vary. System manufacturers may vary configuration, yielding different results. -VGL-04
  2. The benchmark tests were performed on all 1208 Vitis L1 library C-code designs as of February 12th, 2023. All designs were run using a system with 2P Intel Xeon E5-2690 CPUs with CentOS Linux, SMT enabled, Turbo Boost disabled. Hardware configuration not expected to effect software test results. Results may vary based on software and firmware settings and configurations- VGL-03