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Vivado IP Integrator Key Features and Benefits
- Tight Integration within the Vivado Integrated Design Environment
- Seamless inclusion of IP Integrator hierarchical subsystems into the overall design
- Rapid capture and packaging of IP Integrator designs for reuse
- Support for both graphical and Tcl-based design flows
- Rapid simulation and cross-probing between multiple design views
- Support for All Design Domains
- Support for processor or processor-less designs
- Integration of algorithmic (Vitis HLS and Model Composer) and RTL-level IP
- Combination of DSP, video, analog, embedded, connectivity, and logic
- Support for Project based DFX Flow
- Focus on Designer Productivity
- DRCs on complex interface level connections during design assembly
- Recognition and correction of common design errors
- Automatic IP parameter propagation to interconnected IP
- System-level optimizations
- Automated designer assistance
- Enhanced Collaboration Support
- Enhanced Collaboration Support
- Team Based designs using Block Design Container enables reusability and modular designs
- Revision control improvements separating source files from generated files
- Block Design Diff tool to compare two Block Designs
High-Level Design Features
Here's a quick overview of Vivado™ Design Suite features for Accelerating High-Level Design. Click the other tabs for complete feature details..
- Vitis HLS
- IP Integrator
- Abstract Shell
- Vitis Model Composer
Vitis High-Level Synthesis Tool
The advanced algorithms used today in AI, wireless, medical, defense, and consumer applications are more sophisticated than ever before. The Vitis™ High-Level Synthesis tool, included as a no-cost upgrade in all Vivado™ Editions, accelerates IP creation by enabling C++ specifications to be directly targeted into AMD programmable devices without the need for manually creating equivalent RTL designs. The Vitis HLS tool supports both the Vitis and Vivado design environments, and enables software and hardware designers alike to accelerate kernel or IP creation through:
- Abstraction of algorithmic descriptions, data type specifications with fixed-point or floating-point integers, and interfaces (FIFO, memories, AXI4)
- Extensive libraries for including built-in support for arbitrary precision data types, streams, and vectorized data types
- Directive-driven, architecture-aware synthesis with high QoR
- Fast time to QoR that rivals hand-coded RTL
- Accelerated verification using C/C++ test bench simulation and automatic VHDL or Verilog simulation and test bench generation
- Automatic use of AMD on-chip memories and DSP elements, including for floating-point types
Libraries
The following built-in libraries are included with the Vitis HLS tool:
Name | Description |
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Arbitrary Precision Data Types |
Integer and fixed-point (ap_int.h) types |
HLS Streams |
Models for streaming data structures—designed to obtain best performance and area (hls_stream.h) |
Vector types |
Vectorized types and operations (hls_vector.h) including for arbitrary precision types |
HLS Math |
Extensive support for the synthesis of standard C (math.h) and C++ (cmath.h) math libraries. Support includes floating-point and fixed-point functions: abs, atan, atanf, atan2, atan2, ceil, ceilf, copysign, copysignf, cos, cosf, coshf, expf, fabs, fabsf, floorf, fmax, fmin, logf, fpclassify, isfinite, isinf, isnan, isnormal, log, log10, modf, modff, recip, recipf, round, rsqrt, rsqrtf, 1/sqrt, signbit, sin, sincos, sincosf, sinf, sinhf, sqrt, tan, tanf, trunc |
The Vitis HLS tool also supports the Vitis performance-optimized libraries available on GitHub with out-of-the-box acceleration and minimal-to-zero code changes to your existing applications. These common Vitis accelerated-libraries include advanced math, statistics, linear algebra, and DSP to offer core functionalities for a wide range of applications. These libraries offer acceleration for workloads such as vision and image processing with OpenCV functions, quantitative finance, database, data analytics, data compression, and more.
For more information, please visit the Vitis HLS site.