The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ASICs and FPGAs. The IP core supports line speeds up to 32.5 Gbps per lane with 64b66b encoding and includes full backwards compatibility with JESD204B and its 8b10b encoding.
The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
- Full JESD204C feature set available
- Link and transport layer available
- 8B/10B, 64B/66B, 64B/80B encoding/decoding supported
- Scrambling and de-scrambling included
- Support for all subclasses (0, 1, 2)
- Silicon proven
- Lint/CDC optimized
- UVM regression tested
- Interoperability tested with leading PHY/Serdes vendors
- Solid documentation including integration guide
- Easy to use RTL test environment
- Strong engineering support for bring-up
- Targeting any RTL implementation like ASICs, ASSPs and FPGAs