製品説明
Design Gateway SATA3 Host CPUless IP Core is designed to be an all-in-one system that contains the application layer, transport layer, and link layer in one IP. This helps the connection with the PHY layer implemented by the transceiver without CPU and DDR usage. The SATA Physical layer is designed by HDL code for controlling transceiver following SATA protocol and is the interface module connected between SATA3HCTL IP and SATA device. This SATA3 IP core PHY is provided in the reference design in the release stuff for the IP customer. The SATA3 host IP core features dgIF typeS user interface that is very easy to access and comes with control and data interface.
For more detail, please visit http://www.dgway.com/SATA-IP_X_E.html
主な機能と利点
- Simple user interface by dgIF types
- Support four commands such as IDENTIFY DEVICE, SECURITY ERASE UNIT, WRITE DMA (EXT), and READ DMA (EXT)
- SATA application layer, transaction layer and link layer by hardware logic
- No need for external memory and CPU
- Compliant with the Serial ATA specification revision 3.0
- 2 x 4Kbyte FIFO for internal buffer
- Support SATA-III Speed by using 150 MHz for SATA clock and higher frequency for user clock
- Free HDL code of SATA3 PHY and the reference design in release stuff
- Reference design by using AB09-FMCRAID adapter board from Design Gateway
主な資料
