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Vitis Networking P4

作成者: AMD

Vitis Networking P4 is a high-level design environment to simplify the design of packet-processing data planes that target FPGA hardware.

パーツ番号:
- EF-DI-VITISNETP4-PROJ
- EF-DI-VITISNETP4-SITE
- EF-DI-VITISNETP4-WW
- EFR-DI-VITISNETP4-PROJ
- EFR-DI-VITISNETP4-SITE
- EFR-DI-VITISNETP4-WW
デザインツールサポート: Vivado Software
ライセンス: Core License Agreement
デバイスサポート: Kintex UltraScale, Kintex UltraScale+, Versal AI Core, Versal AI Edge, Versal HBM, Versal Premium, Versal Prime, Virtex UltraScale, Virtex UltraScale+, Zynq UltraScale+ MPSoC, Zynq UltraScale+ RFSoC

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Overview
Documentation
Part Numbers

Product Description

Vitis Networking P4 is a high-level design environment to simplify the design of packet-processing data planes that target FPGA hardware. It is a tool to convert the P4 design intent into an AMD FPGA design solution. It allows programmers to build new data planes by explicitly specifying the header and packet processing. It supports processing engines with specialized behavior, to include: parsing engines, match-action engines, and deparsing engines, each generated according to an application-specific requirement. To implement a P4 design the compiler maps the control flow onto a custom data plane architecture of engines. This mapping chooses appropriate engine types and customizes each of them based on the P4-specified processing.

Key Features and Benefits

Construction of hierarchical Vitis Networking P4 systems, consisting of a large variety of different types of engines including: Parsing, Deparsing, and Match-Action engines

Parsing engines extract header information from packets
Deparsing engines manipulate the contents of packet headers by inserting, modifying, or removing packet data
Action engines are designed for manipulating metadata that might be determined from packets or data originating externally or internally from some other engine
Look-up engines instantiate memory search IP cores generated from a library for packet processing including: exact match (BCAM), longest-prefix match (STCAM), ternary match (TCAM), and RAM (direct) tables
Systems resulting in high performance hardware implementations, achieving up to 200 Gb/s
Support for different clock domains so that engines can run at one of the following frequencies:
- Line rate of the packet data bus used typically for engines reading or modifying packets
- Packet rate used for functions that occur once per packet such as an individual look-up
- Control rate which is the speed of the memory-mapped control interface for controlling and configuring engines
Software available for high level system simulation of the design prior to running RTL simulations
System backpressure capability is automatically generated including the insertion of buffers providing dataflow synchronization for engines. This capability enables backpressure of the packet bus for momentarily pausing packet processing
AXI-Stream signaling protocol for packet interfaces

Please contact your local sales representative for more information.

Academic Users

Request an academic license

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

UG1307 - Vitis Networking P4 Installation Guide and Release Notes (UG1307) (v2024.2)

Describes the AMD Vitis™ Networking P4 installation and latest release notes.

View User Guide

UG1308 - Vitis Networking P4 User Guide (UG1308) (v2024.2)

Describes the AMD Vitis Networking P4 IP.

View User Guide

UG1373 - Vitis Networking P4 Getting Started Guide (UG1373) (v2024.2)

Provides information on how to get started quickly and easily.

View User Guide

WP555 - Simplify Packet Processing Design with P4 and Vivado Tools (WP555) (v1.0)

Describes how using the P4 tool can significantly reduce engineering effort while developing FPGA-based packet-processing systems.

View White Paper

Part Number	Description
EF-DI-VITISNETP4-PROJ	LogiCORE™, Vitis Networking P4 Project License
EF-DI-VITISNETP4-SITE	LogiCORE, Vitis Networking P4 Site License
EF-DI-VITISNETP4-WW	LogiCORE, Vitis Networking P4 Worldwide License
EFR-DI-VITISNETP4-PROJ	LogiCORE, Vitis Networking P4 Project License Support Renewal
EFR-DI-VITISNETP4-SITE	LogiCORE, Vitis Networking P4, Site License Support Renewal
EFR-DI-VITISNETP4-WW	LogiCORE, Vitis Networking P4 Worldwide License Support Renewal

_{Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.}

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Vitis Networking P4

Product Description

Key Features and Benefits

Related Product

Academic Users

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