作成者: AMD
The customizable LogiCORE™ IP Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTH transceivers is designed for evaluating and monitoring the GTH transceivers.
The customizable LogiCORE™ IP Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTH transceivers is designed for evaluating and monitoring the GTH transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTH transceivers. Communication logic is also included to allow the design to be run-time accessible through JTAG. This core can be used as a self-contained or open design, based on customer configuration, and as described in this document.
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