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QDMA Subsystem for PCI Express®

作成者: AMD

The AMD QDMA Subsystem for PCI Express® (PCIe®) implements a high performance DMA for use with the PCI Express 3.x Integrated Block with the concept of multiple queues that is different from the DMA/Bridge Subsystem for PCI Express which uses multiple C2H and H2C Channels.

デザインツールサポート: Vivado Software
バンドル内容: Vivado Software
ライセンス: End User License Agreement
デバイスサポート: Kintex UltraScale+, Virtex UltraScale+, Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC

Overview
Documentation
Supported Tool Versions

Product Description

The AMD LogiCORE™ QDMA for PCI Express® (PCIe®) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express Integrated Block. The IP provides an optional AXI4-MM or AXI4-Stream user interface.

The QDMA solution provides support for multiple Physical/ Virtual Functions with scalable queues, and is ideal for applications that require small packet performance at low latency.

Drivers

Reference drivers are available at https://github.com/Xilinx/dma_ip_drivers.

Key Features and Benefits

Supports Integrated Blocks for PCIe in UltraScale+™ devices, including Virtex™ UltraScale+™ devices with HBM

Supports 64, 128, 256 and 512-bit data path
Supports x1, x2, x4, x8, or x16 link widths.
Supports Gen1, Gen2, and Gen3 link speeds
Support for both the AXI4-Memory Mapped and AXI4-Stream interfaces per queue
2K queue sets
- 2K H2C Descriptor rings
- 2K C2H Descriptor rings
- 2K C2H Write back rings
Supports Polling Mode (Status Descriptor Write Back)
C2H Stream interrupt moderation
C2H stream CMPT entry coalesce
Descriptor and DMA Customization through user logic
- Allow Custom Descriptor format
- Traffic Management
Supports SR-IOV up to 4 Physical Functions and 252 Virtual Functions
- Thin Hypervisor model
- Allows only privileged/Physical function (PF) to program contexts and registers
- Function Level Reset support
- Mailbox
Interrupts
- 2K MSI-X vectors
- Up to 8 MSI-X per function
- Interrupt coalescing

Resource Utilization

Queue DMA Subsystem for PCI Express Resource Utilization

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

PG302 - QDMA Subsystem for PCI Express Product Guide (PG302) (v5.0)

Implements a high performance DMA for use with the 3.x Integrated Block for PCI Express® with the concept of multiple queues that is different from the DMA/Bridge Subsystem for PCI Express, which uses multiple C2H and H2C channels.

View Product Guide qdma-v5-0-register-map.zip