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Digilent ZedBoard

Overview

XUP is offering the Digilent ZedBoard, a Zynq based community board, at affordable academic price. The board comes with several user interfaces that can be accessed through the Zynq processing system and through the programmable logic. Users can build and include hardware accelerators in the programmable logic  to meet bandwidth demanding applications, combined with  industry leading ARM processor, lending itself to innovative, yet practical, applications in education.

What is included?

  • The ZedBoard featuring the XC7Z020T-1CSG324 adaptive SoC
  • 12V power supply with USA and European adapters
  • 4 GB SD Card
  • Micro-USB cable
  • USB Adapter: Male Micro-B to Female Standard-A
  • Getting Started Guide
  • Vivado Design Suite: WebPack Edition DVD with device-locked Vivado Logic Analyzer license

Suggested use of this board

  • Teach and conduct research in the areas of
    • Automotive applications
    • Computer architecture
    • Embedded Linux OS development
    • Embedded processing systems
    • Hardware/software co-design
  • Build and include hardware accelerators to meet bandwidth demanding applications

Zynq-7000 SoC Features

  • Dual ARM® Cortex™-A9 MPCore™ with CoreSight™
  • 32 KB Instruction, 32 KB Data per processor L1 Cache
  • 512 KB unified L2 Cache
  • 256 KB On-Chip Memory
  • 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
  • 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO on-chip peripherals
  • 85K logic cells (13300 logic slices, each with four 6-input LUTs and 8 flip-flops)
  • 560 Kbits of fast block RAM
  • Four clock management tiles, each with phase-locked loop (PLL)
  • 220 DSP slices
  • Internal clock speeds exceeding 450MHz
  • 2x 12 bit, 1 MSPS On-chip analog-to-digital converter (XADC)
Hardware

Key Features

Feature Description
FPGA
  • Zynq-7000 AP SoC XC7Z020-1CLG484
I/O Interfaces
  • USB-UART for programming and serial communication
  • One 10/100/1G Ethernet
  • USB OTG 2.0
  • USB-UART bridge
  • 12-bit VGA output
  • HDMI Output
  • I2S CODEC
  • Audio Line-In, Line-Out, headphone, microphone
Memory
  • 512 Mbyte DDR3
  • 256 Mbit Quad-SPI Flash
  • SD card connector
Displays
  • One 128x32 OLED
Switches and LEDs
  • 8 Slide switches accessible from PL
  • 8 LEDs accessible from PL
  • 1 LED accessible from PS
  • 5 Push-buttons accessible from PL
  • 2 Push-buttons accessible from PS
  • 1 Reset button accessible from PL
  • 1 Reset button accessible from PS
Clocks
  • One 100 MHz Oscillator for PL
  • one 33.333 MHz Oscillator for PS
Expansion ports
  • One LPC FMC
  • One AMS Header
  • One header for XADC signals
  • 5 Pmod ports
Tools & IP
Vivado Design Suite: WebPack Edition The Vivado Design Suite WebPACK™ Edition is the FREE version of the revolutionary design suite.  Vivado WebPACK delivers instant access to some basic Vivado features and functionality at no cost.
Vivado Design Suite: System Edition The Xilinx Vivado™ Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for programmable devices.
ISE Design Suite: WebPack Edition ISE® WebPACK™ design software is the industry´s only FREE, fully featured front-to-back FPGA design solution for Linux, Windows XP, and Windows 7. ISE WebPACK is the ideal downloadable solution for FPGA and CPLD design offering HDL synthesis and simulation, implementation, device fitting, and JTAG programming. ISE WebPACK delivers a complete, front-to-back design flow providing instant access to the ISE features and functionality at no cost.
ISE Design Suite: System Edition

ISE® Design Suite is the Industry-proven solution for Xilinx programmable devices including 7 series (and pre-7 series devices) and Zynq™-7000 SoC.  It facilitates designing and verification of digital circuits in the application areas of pure logic design, embedded system design, digital signal processing, communication by providing tools such as ChipScope Pro, Embedded Development Kit, Software Development Kit, System Generator for DSP, and High-Level Synthesis. 
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