XUP PYNQ-Z1
PYNQ- Python Productivity for Zynq
PYNQ is an open-source project from Xilinx that makes it easy to design embedded systems with Zynq All Programmable Systems on Chips (APSoCs). Using the Python language and libraries, designers can exploit the benefits of programmable logic and microprocessors in Zynq to build more capable and exciting embedded systems.
What is included?
- The PYNQ-Z1 board featuring the ZYNQ XC7Z020-1CLG400C All Programmable SoC
Additional Required Items
- The pynq image and 8 GB SD Card
- Micro-USB cable
- Ethernet cable
Zynq-7000 All Programmable SoC Features
- Dual ARM® Cortex™-A9 MPCore™ with CoreSight™
- 32 KB Instruction, 32 KB Data per processor L1 Cache
- 512 KB unified L2 Cache
- 256 KB On-Chip Memory
- 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
- 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO on-chip peripherals
- 85K logic cells (13300 logic slices, each with four 6-input LUTs and 8 flip-flops)
- 630 KB of fast block RAM
- Four clock management tiles, each with phase-locked loop (PLL)
- 220 DSP slices
- Internal clock speeds exceeding 450MHz
- 2x 12 bit, 1 MSPS On-chip analog-to-digital converter (XADC)
Key Features
| Feature | Description |
| FPGA |
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| I/O Interfaces |
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| Memory |
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| Switches and LEDs |
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| Clocks |
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| Expansion ports |
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| Download PYNQ Image | The PYNQ image is a bootable Linux image, and includes the pynq Python package, and other open-source packages. |
| Vivado Design Suite: WebPack Edition | The Xilinx Vivado™ Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for all programmable devices. One of the editions, WebPACK™, is FREE to download and provides access to Vivado features and functionality at no cost. It can be used to update the base overlay or create a new overlay. |
Documentation
- Please see the PYNQ ReadtheDocs webpage
Additional Information and Supporting Material
- Please visit the PYNQ project webpage