FPGA Design Flow using ISE
|Course Description||This course provides professors with an introduction to designing with Xilinx FPGAs using ISE® Foundation™ software.|
|Who should attend?||Professors who are new to FPGAs or Xilinx technology and wish to use Xilinx All Programmabe devices in digital design|
After completing this workshop, you will be able to:
- Describe the general FPGA architectures and the design flow
- Configure FPGA architecture features, such as DCM, using the Architecture Wizard
- Communicate design timing objectives through the use of global timing constraints
- Pinpoint design bottlenecks using the reports
- Utilize synthesis options to improve performance
- Understand the various implementation options
- Create and integrate IP cores into your design flow using CORE Generator™ software
- Use ChipScope™ Pro tool to perform on-chip verification
- Use the 8-bit PicoBlaze™ microcontroller to interface to various board components
- Basic FPGA Architecture
- Xilinx Tool Flow
- Lab 1: Xilinx Tool Flow
- An introduction to FPGA design flow. Open a project containing the PicoBlaze 8-bit microcontroller and simulate the design using the ISim HDL simulator provided with the ISE Foundation software.
- Architecture Wizard and Pins Assignment
- Lab 2: Architecture Wizard and Pins Assignment
- Use the Architecture Wizard to configure and instantiate a DCM into a PicoBlaze design. Assign pin locations with PACE. Implement design to generate a bitstream file. Download and test in hardware using hyperterminal.
- Reading Reports
- Global Timing Reports
- Lab 3: Global Timing Constraints
- Enter and analyze the effects of global timing constraints on a simple PicoBlaze design. Download and test the design in hardware using hyperterminal.
- FPGA Design Techniques
- Synchronous Design Techniques
- Synthesis Techniques
- Lab 4: Synthesis Techniques with Xilinx Synthesis Technology (XST)
- Set various synthesis options to improve results for a simple PicoBlaze design. Download the design and test in hardware using hyperterminal.
- Implementation Options
- Core Generator System
- Lab 5: CORE Generator Software
- Generate the instruction ROM for a PicoBlaze design using CORE Generator, initialized with instructions generated from the PicoBlaze assembler. Download and test in hardware.
- ChipScope-Pro Tool
- Lab 6: ChipScope-Pro Tool
- Use the ChipScope-Pro tool to debug a simple PicoBlaze design using an Integrated Logic Analyzer (ILA) core.