製品説明
The MIPI I3C interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compatibility. This standard offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems.
Arasan's IP is also available to license for ASIC applications.
Tools used Vivado 2022.1Arasan offers a licensing scheme to go from FPGA to ASIC at reduced license fees.
Customers can migrate to
ASIC by licensing Arasan’s I3C CONTROLLER & I3C PHY IP core for ASIC.
主な機能と利点
- Compliant with MIPI I3C Specification V1.0
- Compliant with MIPI I3C HCI Specification V1.0
- Supports up to 12.5 MHz operation using Push-Pull
- Open-Drain and Push-pull type transactions (as required)
- Supports legacy I2C devices
- Dynamic Addressing while supporting Static Addressing for Legacy I2C devices
- Legacy I2C Messaging
- I2C-like Single Data Rate Messaging (SDR)
- Optional High Data Rate Messaging Modes (HDR)
- Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present)
- Reception of In-band Interrupt Support from the I3C Slave devices
- Reception of Hot-Join from newly added I3C Slave devices
- Synchronous Timing Support and Asynchronous Time Stamping.
- APB/AHB Target Interface for Configuring/Controlling the IP with Interrupt output
- Small 16-byte (Configurable) FIFO for transferring data between Master and the Slave devices
- Independent Clocks for AHB and the I3C Interface
