製品説明
This LDPC IP core consists of an LDPC encoder and FAID™ decoder achieving a maximum decoding throughput of 6.5Gbytes/s for NAND flash controllers transitioning to support the next generation of NAND flash memories (such as 3D TLC, 3D QLC, and beyond). Both the encoder and decoder are based on proprietary and patented algorithms, and are included as separate synthesizable cores. The decoder performs hard-decision decoding and 2-bit soft-decision decoding (1 bit soft) in a single architecture. The FAID™ decoder provides increased error correction with a gain of 10%-15% in raw bit error rate (RBER) compared to min-sum-based decoders, while ensuring that a very low uncorrectable bit error-rate (UBER) of 1e-17 and lower is achieved with no error floor. Unlike standard LDPC decoders, the FAID™ decoder does not use a log-likelihood-ratio (LLR) table and provides robustness to the choice of soft reads leading to a simplified NAND media management for the flash controller.
The IP core has been validated in hardware and also with data collected from performing NAND characterization on 3D TLC and 3D QLC NAND chip samples.
主な機能と利点
- Guaranteed to achieve very low frame error rate (FER) with no error floor.
- ECC Performance (4KB, R=0.89):
Hard-decision decoding: RBER=0.0067 @ FER =1e-6 (UBER =3e-11), RBER = 0.0058 @ FER=1e-11 (UBER=3e-16)
2-bit soft-decision decoding (1 bit hard + 1 bit soft): RBER=0.0151 @ FER =1e-6, RBER = 0.0139 @ FER=1e-11
- ECC Performance (4KB, R=0.86):
Hard-decision decoding: RBER=0.0097 @ FER=1e-6, RBER=0.0087 @ FER=1e-11
2-bit soft-decision decoding (1 bit hard + 1 bit soft): RBER=0.0202 @ FER=1e-6, RBER=0.0190 @ FER=1e-11
- Max Throughput @500MHz (4KB, R=0.89):
Decoder - 6.5Gbytes/s; Encoder - 4.3Gbytes/s
- The total resource usage of the IP core (which includes the encoder and decoder) is provided in the product specs for a sample code configuration of 4KB, R=0.89.
- Customizable for a different information length (1KB, 2KB, 4KB) + metadata and code rate (0.83 to 0.95).
- Option to add feature to support multiple code rates in the same IP core to provide flexibility to change the code rate during processing.
- Options to customize the interface and any other features of the core.
