製品説明
TOE25G-IP core (TCP Off-loading Engine) is the pure hardware logic TCP/IP protocol stack engine without CPU. TOE25G-IP provides 2.5X the performance of 10GbE over single channel fiber optic cable. Maximize performance per channel, provide better network traffic density and scalability, giving the greater cost-effective or power-efficient per BIT than traditional 10GbE/40GbE network technology. This IP product includes reference design for AMD FPGA. It helps you to reduce development time. Design Gateway provide demo file for AMD FPGA boards. You can evaluate TOE25G-IP core on real board before purchasing.
主な機能と利点
- TCP/IP off-loading engine for 10/25GBASE-R
- Support IPv4 protocol
- Support one port connection (Support Multi-session by implementing multiple cores)
- Supports Full Duplex communication
- Support both Server and Client mode (Passive/Active open and close)
- Support Jumbo frame
- Transmitted packet size aligned to 128-bit, bus size of transmit data
- Total received data size aligned to 128-bit, bus size of received data
- Transmit/Receive buffer size, programmable on HDL for optimized resource
- All pure hardware TCP/IP protocol stack
- Simple control interface by 32-bit Register interface & Simple data interface by 128-bit FIFO interface
- 64-bit AXI4 stream to interface for 10G/25G Ethernet MAC
- User clock frequency must be more than or equal to 195.3125 MHz for 25Gb Ethernet
- Support 10GbE by using DG 10G25G EMAC-IP and PCS
- Provide free evaluation bit file for FPGA Development Kits
- Reference design is included in IP core product
主な資料
