製品説明
XIP3030C is a compact IP core designed for versatile support of all variants of the SHA-3 hash function and related extendable-output function SHAKE as well as the SHA-3 derived function cSHAKE and its variants KMAC, TupleHash and ParallelHash.
SHA-3 and SHAKE are defined in the NIST (National Institute of Standards and Technology) standard FIPS PUB 202 and cSHAKE, KMAC, TupleHash and ParallelHash are specified in NIST Special Publication 800-185.
XIP3030C consumes only small amounts of FPGA resources that allows it to be used even
in settings where resources are scarce
XIP3030C has also been successfully validated in the CAVP (Cryptographic Algorithm Validation Program) by NIST (National Institute for Standards and Technology).
主な機能と利点
- Minimal Resource Requirements: XIP3030C requires only 978 LUT6 in the AMD Artix 7.
- Versatile Algorithm Support: XIP3030C supports SHA-3-224/256/384/512, SHAKE-128/256, cSHAKE-128/256, KMAC, TupleHash and ParallelHash
- Secure Architecture: The execution time of XIP3030C is independent of the input values and, consequently, provides full protection against timing-based side-channel attacks.
- Standard Compliance: XIP3030C is compliant with FIPS 202 and SP 800-185.
- Easy Integration: The 64-bit interface of XIP3030C supports easy integration with software and/or additional FPGA design.
- CAVP validated
主な資料
