This overview outlines the features and product selection of the Virtex-4QV FPGAs.

Space-Grade Virtex-4QV FPGAs: DC and AC Switching Characteristics

VIRTEX 4_XQ4VXL60-EF668 100% Material Declaration Data Sheet

Aerospace and Defense Bumping Supplier Change: Virtex®-4QV Space-Grade Devices Using Ceramic Flip-Chip Column Grid, Qualification Report

Virtex-4 FPGA User Guide

XtremeDSP for Virtex-4 FPGAs User Guide

Virtex-4 QV FPGA Ceramic Packaging and Pinout Specifications

Single-Event Upset Mitigation Design Flow for Xilinx FPGA PowerPC Systems

Describes avionics full-duplex switched Ethernet (AFDX) as defined in the ARINC Specification 664, Part 7.

Xilinx Virtex-4 and Virtex-5 devices a have high-precision programmable delay element associated with every input pin. These delay elements, called IDELAY, can be used to implement an oversampler that uses very few FPGA logic resources and, more importantly, just a single DCM and two global clock resources to do 8X oversampling. This solution provides better jitter tolerance than techniques that use multiple DCMs.

Single-Event Upset Mitigation for Xilinx FPGA Block Memories

Single-Event Upset Mitigation Selection Guide

The purpose of this notification is to announce qualification of new second source construction materials, and the addition of a second source supplier for Xilinx plastic flip-chip products. In addition, a mask set stepping introduction for select Virtex -4 FX products.

This notification is to inform you of the Xilinx test site transfer of all Aerospace Defense “XQ” I-grade and M-grade devices from Xilinx San Jose, California “XSJ” and/or Xilinx Dublin, Ireland “XIR” test sites to Xilinx Singapore “XAP” test site.

To announce conversion of substrate material changed from BT to ABF build-up for selected Aerospace Defense "XQ" Virtex -4 FPGA device/package.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To announce that Xilinx has qualified a new bumping supplier for Virtex -4QV FPGA space-grade devices in ceramic flip chip column grid array (CF) packages.

To inform Xilinx customers of the removal of Xilinx support for Parity Checking for PowerPC 405 in all Virtex -4 FX FPGAs for the "XC" Commercial "C", Industrial "I", and Aerospace/Defense "XQ" devices.

To communicate that Xilinx is changing the lid size used on the XQR5VFX130-1CF1752V and B grade products. In addition Xilinx will be changing at a later date the lid sizes used for the XQR4VFX60-10CF1144V, XQR4VSX55-10CF1140V, XQR4VLX200-10CF1509V and the XQR4VFX140-10CF1509V products.

This notification is to notify customers of a product marking change for some Xilinx FPGA products.

To communicate that Xilinx is discontinuing the current Virtex -4 and Virtex -5 QV FPGA Ceramic Flip Chip Column Grid Array (CF package code) parts due to current supplier line discontinuance. However, Xilinx will continue to offer Virtex-4 and Virtex-5 QV FPGA Ceramic Flip Chip Column Grid Array products under a new CN package code with a new assembly supplier.

To inform customers that Xilinx is adding a new logistics service provider for our products.

The purpose of this notification is to communicate substrate material change for Virtex®, Virtex®-II, Virtex®-II Pro, Virtex®-4 and Virtex®-5 FPGA packages.

Virtex®、Virtex®-II、Virtex®-II Pro、Virtex®-4、および Virtex®-5 FPGA パッケージのサブストレート材が変更されることをお知らせするものです。

The purpose of this notification is to communicate that Xilinx will continue supplying Eutectic bump from an additional bump factory at Siliconware Precision Industry Ltd. (SPIL) for the next few coming years for all Virtex -II Pro, Virtex -4, Virtex -5 and Virtex -6 FPGAs defense-grade “XQ” flip-chip products. As described in XCN16003, Xilinx has also qualified defense-grade 7 Series XQ FPGA product on the additional bump facility.

The purpose of this notification is to communicate that Xilinx will continue supplying Eutectic bump from an additional bump factory at Siliconware Precision Industry Ltd. (SPIL) for the next few coming years for all Virtex -4 and Virtex -5 FPGA space-grade “QV” flip-chip products. As described in XCN16003 and XCN18018, Xilinx has also qualified defense-grade FPGA products from this additional bump facility.

Announces that AMD-Xilinx is converting the bump to lead-free for Virtex-4/-5/-6 and Series 7 FPGAs Defense (XQ) and Space (XQR) flip-chip products.

The purpose of this notification is to communicate that Xilinx® is discontinuing selective Defense (XQ) and Space (XQR) FPGA products. This product discontinuance notice applies to all speed and temperature-grade variations.

Xilinx space-grade products are leading the aerospace industry to a new era of re-programmability and performance. The portfolio of rad-hard and rad-tolerant re-configurable FPGAs and configuration memories provide unmatched reliability, flexibility, density, and system level architectures that enable unparalleled design cycle and cost benefits for space systems.