2. IP 核
  3. FIR Compiler

FIR Compiler

概述

产品描述

Finite Impulse Response (FIR) Filter 是 DSP 系统内最常见和最基础的构建模块之一。尽管它的算法非常简单，但实现细节上的变异可能也很大，对于今天的硬件工程师来说，会耗费大量的时间，尤其是在数字无线电等滤波器控制系统中。FIR 编译器不仅可缩短按下按钮的滤波器实现时间，同时还可为用户提供在 FIR 滤波器规范的不同硬件架构之间进行权衡的能力。

主要功能与优势

  • 提供带有 CORE Generator 的 VHDL 演示测试台
  • 支持基于乘法累加 (MAC) 的流水线直接形式 FIR 和基于转置直接形式的 MACFIR
  • 高性能有限脉冲响应 (FIR)、多相抽取滤波器、多相内插器、半带、半带抽取滤波器和半带内插器、Hilbert 变换和内插式滤波器实现方案
  • 高级交叉通道，有助于为高级系统实现可配置的带宽特性
  • 支持多列 DSP48/DSP58 切片以实现对称滤波器
  • 一个定点位精确的 C 模型，可为 Xilinx FIR 编译器内核实现系统级分析
  • 多种实现架构：DAFIR、基于加法器结构树的 MACFIR（适用于支持 Mult18x18 的器件）和基于加法器链的 MACFIR（适用于支持 XtremeDSP™ Slice 的器件）
  • Versal 器件（-1LP 速度等级）可实现高达 680MHz 的性能
  • 支持 2 -2048 抽头
  • 为最紧凑的实现方案提供硬件折叠的自动控制
  • 支持多达 64 个通道（通道 = 独立语音/数据/视频流），与 FPGA 同时处理的其它流媒体内容无关。
  • 内插和抽取因子通常多达 64 个，单通道滤波器多达 1024 个
  • 支持可重新加载的系数以及达 16 个系数集
  • 系数结构自动优化，减少面积消耗：对称和半带
  • 为数据及系数存储自动选择模块与分布式内存
  • 与 Vivado™ IP Integrator、Vivado IP Catalog 和 AMD System Generator for DSP™ 结合使用
  • 支持超级采样率滤波器配置
  • 与 Vivado IP Integrator、Vivado IP Catalog 和 Vitis Model Composer 联用

资源利用率

技术支持

器件系列:

设计工具:

技术文档

主要资料

Default Default 标题 文件类型 日期
开始设计

1. Choose your IP Solution

Choose the AMD FIR Compiler for applications that need a filter and a wide range of features.  For more information refer to the FIR Compiler Product Page or to the Features section of the FIR Compiler Product Guide (PG149).

2. Configure the IP

Before configuring the FIR Compiler, use a Filter Design tool, such as MATLAB®, to generate coefficients for the application.

Once you have the coefficients, configure the IP customization options. For details, the Customizing and Generating the Core section in the Design Flow Steps chapter of the FIR Compiler Product Guide (PG149).

Start by configuring the following options:

  • Filter Options Tab:
    • Filter Coefficients - Enter your coefficients generated in your Filter Design tool.
    • Filter Specification - Select the Type of Filter Implementation.
  • Channel Specification Tab:
    • Hardware Oversampling Specification.
    • Set the Input Sample Rate and the Clock Frequency.
  • Summary Tab:
    • Review the Summary of Configuration.

In addition, review the following tabs on the left side of the GUI:

  • Freq. Response: This enables you to verify that the frequency response matches your filter design requirements.
  • Implementation Details: This enables you to see the resources consumed by your filter configuration.

After the IP has been configured, generate the IP solution.

3. Generate the Example Design for a Demonstration Board

The FIR Compiler generates an example test bench along with the IP. Information on the test bench can be found in the Test Bench chapter of the FIR Compiler Product Guide (PG149). The best way to test a FIR Compiler implementation is to implement an impulse and review the impulse response in simulation. Many simulation tools allow formatting of the output in an analog format, which will give a visual view of the impulse response that can be reviewed in addition to the data response.

4. Integration

Now you are ready to integrate the FIR Compiler into your own application. The user interface is described in the Port Description section in the Product Specification chapter of the FIR Compiler Product Guide (PG149). Review the simulation in Step 3 as a reference on the expected waveforms for the interface ports.

Getting Started Resources