ザイリンクスの開発専門家たちは、一連のチュートリアルや研究論文、プレゼンテーションなどを提供して、高速シリアル デザイン、シグナル/パワー インテグリティ、メモリ インターフェイシングなどさまざまな技術分野におけるシステム設計の問題解決方法を共有しています。
Design of Flyover QSFP (FQSFP) Design for 56+Gb/s (論文) (プレゼンテーション)
End-to-End System-Level Analyses for PCIe-4.0 (論文) (プレゼンテーション
Characterization of DDR4 Receiver Impact on Post-Equalization Eye (論文) (プレゼンテーション)
112G Serial Transmission over Copper PAM4 vs PAM8 Signaling (論文) (プレゼンテーション)
IBIS-AMI Modeling and Simulation of using Duobinary Signaling (論文) (プレゼンテーション)
IBIS-AMI Modeling of Asynchronous High Speed Link Systems (論文) (プレゼンテーション)
DESIGNING TO EVOLVING LTE ADVANCED PRO ANDPRE-5G REQUIREMENTS (チュートリアル)
A Tutorial on PAM4 Signaling for 56G Serial Link Applications (チュートリアル)
32G to 56G Link Analysis and Optimization for Pathological Channels (チュートリアル)
Investigation of Package Crosstalk and Impact to 28Gbps Transceiver Jitter Margin (論文)
Novel Methodology of IBIS-AMI Hardware Correlation Using Trend and Distribution Analysis for High-Speed SerDes System (論文) (プレゼンテーション)
Optimal DDR4 System with Data Bus Inversion (論文) (プレゼンテーション)
25G Long Reach Cable Link System Equalization Optimization (論文) (プレゼンテーション)
PAM4 Signaling for 56G Serial Link Applications – A Tutorial (プレゼンテーション)
UltraScale DDR4 De-Emphasis and CTLE Feature Optimization with Statistical Engine for BER Specification (プレゼンテーション)
IBIS-AMI Model Simulations Over Six EDA Platforms (プレゼンテーション)
IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems (プレゼンテーション)
Co-Design for 1TB System Utilizing 28Gbps Transceivers in 20nm Technology (論文)
A Cure for Intra-Pair Skew in High Speed Differential Signals (プレゼンテーション)
UltraScale FPGA DDR4 2400 Mbps System Level Design Optimization and Validation (プレゼンテーション)
Relating COM to Familiar S-Parameter Parametric to Assist 25Gb/s System Design (プレゼンテーション)
Hands-On Tutorial for Fixture Removal of 28Gb/s Tx Measurements (Zip ファイル)
Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (論文) (プレゼンテーション)
Distributed Modeling and Characterization of On-Chip/System Level PDN and Jitter Impact (論文) (プレゼンテーション)
Method for Analytically Calculating BER (Bit Error Rate) in Presence of Non-Linearity ({論文) (プレゼンテーション)
Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems (論文) (プレゼンテーション)
High Speed Serial Link Simulation Based on Dynamic Modeling (論文) (プレゼンテーション)
Comprehensive Full-Chip Methodology to Verify Electromigration and Dynamic Voltage Drop on High Performance FPGA Designs
in the 20nm Technology (論文) (プレゼンテーション)
De-Mystifying the 28 Gb/s SERDES Channel - Design to Measurement (論文) (プレゼンテーション)