製品説明
The Managed Ethernet Switch (MES) IP is a tri-speed (1GE; 100M; 10M) scalable and highly-optimized Ethernet Switch implementable on AMD FPGA families . The switching structure is based on a full-crossbar non-blocking interconnection matrix between the ports. This approach ensures wire-speed frame processing and very low latency times.
The IP includes optional features like IEEE 1588 Transparent Clock, Jumbo Frames, and VLAN tagging and filtering.
It also supports 2.5/5/10Gbps speed for implementing uplink ports.
主な機能と利点
- IEEE 1588v2 Transparent Clock functionalities supported by hardware (P2P-E2E)
- Automatic MAC addresses learning and aging
- Optimized to require few logic resources in order to allow the implementation on low-cost FPGA devices
- Very reduced Latency Times thanks to SoCe proprietary MAC address matching mechanism
- Flexible: Fully scalable and configurable: Number of ports, MAC address Table Length, Buffers queue length, IEEE Transparent Clock functionalities
- High Performance Switching: Full-crossbar matrix among ports implemented to allow maximum throughput
- Tri-speed support: Automatic 10/100/1000 speed recognition
- Flexible Management port via AXI4, MDIO, UART or Configuration-over-Ethernet
- VLAN support
- VLAN Priorities support
- 10/100/1000baseTX FX support
- From 3 up to 32 ports
- Protocol based queueing
- RSTP and MRP support
- DLR support: Supervisor node and Beacon based node
- 2.5G/5G/10G support for uplink ports
- Port Mirroring support
- Per port frame rate limiting
- Cut-Through support
- Static Link Aggregation (802.1AX)
主な資料
