製品説明
The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The core is also suitable for the implementation of controllers for the Power Management Bus (PMBus).
The core can be programmed to operate either as a bus master or a slave, and it is easy to program and integrate. An arbitration mechanism allows operation in a multiple master bus and the SMBus provisioned clock synchronization mechanism allows fast-master/slow-slave communication. Furthermore, the core detects timeout and errors to prevent bus deadlocks, and can filter out glitches on the serial line. The control, status, and data registers of the I2C-SMBUS core are accessible via an AMBA APB or a generic memory mapped interface.
The I2C-SMBUS is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design uses rising-edge-triggered flip-flops only with the reset type (i.e. asynchronous and/or synchronous) being configurable at synthesis time. Furthermore, the core does not use tri-states; therefore scan insertion is straightforward.
主な機能と利点
- Operation Modes: Master Transmitter Mode, Master Receiver Mode, Slave Receiver Mode, Slave Transmitter Mode
- I2C/SMBUS Features: Seven-bit Addressing - Byte-wide Transfers - Bus Arbitration – Clock signal (SCL) generation (in master mode) and data synchronization - START/STOP Timing detection and generation
- Special Features: Timeout/Bus error detection - Clock-Low Extension to allow fast-master slow-slave communication - Configurable glitches filter for clock and data serial lines - Bus status reporting
- Host Interfaces: 32-bit APB or 8-bit generic (8051-like) for register access
- Standards Compliance: Phillips I2C, SMBus and PMBus
主な資料
