製品説明
The SHA-3 IP core is a high-throughput, area-efficient hardware implementation of the SHA-3/Kaccak cryptographic hashing functions, compliant to NISTS’s FIPS 180-4 and FIPS 202 standards.
The core can implement all four fixed-length hash functions (i.e. the SHA3-224, SHA3-256, SHA3-384, and SHA3-512) and both extendable output functions (i.e. SHAKE-128 and SHAKE-256) provisioned by the standards. The function can be dynamically selected at run-time. It’s throughput can optionally be optimized by using input message buffering, which allows it to receive new input while still processing the previous message. Also, the number of hashing rounds per clock is configurable at synthesis time, allowing users to constrain performance to save silicon resources when desired.
The SHA-3 IP core can ensure data integrity and/or user authentication in a range of applications including IPsec and TLS/SSL protocol engines, encrypted data storage, secure processing systems, e-commerce, and financial transaction systems.
主な機能と利点
- Supported Standards: FIPS 202/SHA-3 - Permutation-Based Hash and Extendable-Output functions & FIPS 180-4/Secure Hash Functions (limited to SHA-3 use)
- Configuration Options: Bit-width of input and output data buses, number of input buffers, and number of permutations per cycle
- Functionality: SHA-3 Hash accelerator, with run-time programmable hashing function
- Throughput: Upto 16Gbps per core instance on Kintex Ultrascale+ (lowest speed grade)
- FPGA Resources: From 4,800 LUTs to 20,000 LUTs depending on configuration
主な資料
